M66596 datasheet(11/133 Pages) RENESAS

11 / 133 page

M66596FP/WG

rev .1.00

2006.3.14

page 9 of 127

1.6 Block diagram

The controller is consists of an analog front end unit (AFE), a protocol engine unit (Prtcl_Eng) that includes an SIE,

a pipe control unit (Pipe_Ctrl), a transaction schedule control unit(Schedule Ctrl), a FIFO port unit (FIFO_Port), a

buffer memory unit (Buf_Mem), an interrupt control unit (Int_Ctrl), a bus interface unit (BIU), and a CPU interface

When data is being sent and received between M66596 and a USB peripheral(or host) controller connected on the

USB bus, a buffer memory assigned to each of the pipes is used. Two-way communication is possible by the controller

changing data stored in the buffer memory into USB data packets and outputting them to the USB bus using serial

output, and by inputting data packets on the USB bus which are then stored in the buffer memory.

A6(/ALE), A5-1,

D15-7, D6-1(/AD6-1), D0,

CS_N, RD_N,

WR0_N,WR1_N

MPBUS

CPU bus interface

INT_N, SOF_N

CPU_IF_Reg

Interrupt / SOF output

I/O power supply

Core power supply

AFE power supply

Ground

AFE ground

VDD

VIF

AFEA33V, AFED33V

AFEA15V, AFED15V

AFEA33G,AFED33G

AFEA15G,AFED15G

DGND

USB interface

Split bus

SD7-0

DP, DM

DREQ0_N, DREQ1_N

DACK0_N,

DACK1_N/DSTB0_N,

DEND0_N, DEND1_N

DMA interface

VBUS monitor

VBUS

System control

RST_N, TEST

Reference resistance

REFRIN

Clock

XIN, XOUT

Schedule

_Ctrl

Figure 1.4 Block diagram

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