January 28, 2014

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IDTP9167

Advanced Datasheet

THEORY OF OPERATION

OVERVIEW

The IDTP9167 is a 2MHz switching regulator operating as a controlled current-source. The IDTP9167 is used to increase the

output current capability of the host PMIC’s integrated Buck regulator rails. It is also used by the host PMIC to implement

additional Buck outputs when connected to the PMIC’s integrated controllers. The device communicates with the host PMIC

via a proprietary 2-wire digital bus composed of the DIO and DIF signals. Up to four devices can be connected to the bus to

provide an additional 22A of output current capability to the voltage rail. A device identification resistor connected to the RSET

pin is used by each DPU to set the device ID which determines the switching phase of the particular device. During device

start-up, a 12µA current source is applied to the RSET pin. The voltage generated by the resistor is measured by the DPU

and decoded to extract the ID information. For the case when the DPUs are connected to the host PMIC’s integrated

controller, the same ID setting must be used for all devices in order to support PFM mode operation. In this configuration,

multi-phase operation is not available since all DPUs switch at the same time.

Multiple DPUs combined with the host PMIC have the ability to activate and shed phases seamlessly while continuously

supplying the desired current to the load. Phase-shedding is not supported when the DPUs are connected to the PMIC’s

integrated controller.

Other abilities of the IDTP9167 include current limit control and thermal shutdown.

DIO/DIF INTERFACE DESCRIPTION

General

The DIO and DIF bus attaches the host PMIC to up to four IDTP9167 DPUs to provide control and exchange status

information. A dedicated DIO/DIF pair is utilized for each output rail. The DIO signal is primarily used to convey configuration

information and provide handshake between the host and the DPUs. It also serves as the device master enable as well as the

ON/OFF control for individual phases. The DIF signal provides timing and synchronization for DIO data as well as controls the

output current of the DPUs through duty-cycle modulation. The LX switching frequency is derived from the DIF clock

frequency. When the voltage rail is switched-off, the DIF signal is low and inactive. When the rail is switched-on and one or

more DPUs are active and switching, the DIF clock runs at 4MHz. In idle condition, when the voltage rail is still enabled but all

DPUs have been phase-shed, the DIF clock lowers to 1MHz frequency to save power while maintaining synchronization which

is required to support immediate phase activation during a load step. To ensure robust operation in the presence of noise,

interference and ground bounce, error correction circuitry is employed to ignore glitches, runt pulses, and invalid phase and

duty-cycle presented at the DIF input.

Initialization

During initialization, the host first asserts the DIO signal to enable the DPUs. The individual DPUs then starts up and

immediately reads the connected RSET resistor value to determine its phase ID. The host PMIC then queries the bus to

determine the number of DPUs attached, and individual DPUs respond with their respective IDs. For robustness, the query

process is repeated to confirm consistent response from all DPUs. Once the host has determined the number of DPUs

present, the information is broadcast to all DPUs so individual DPUs can configure their phasing appropriately. The phases

are distributed evenly across the entire switching period. If more than one DPU have the same phase ID, then the host will

treat them as a single DPU, and those phases will be synchronous.