21

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

NOTES:

1. Retransmit setup is complete after OR returns LOW.

2. No more than D –2 words may be written to the FIFO between Reset (Master or Partial) and Retransmit setup. Therefore, IR will be LOW throughout the Retransmit setup

procedure. D = 8,193 for the IDT72255LA and 16,385 for the IDT72265LA.

3. OE = LOW

4. W1, W2, W3 = first, second and third words written to the FIFO after Master Reset.

5. OR goes LOW at 60 ns + 2 RCLK cycles + tREF.

Figure 12. Retransmit Timing (FWFT Mode)

Figure 13. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)

tREF

tRTS

tENH

4670 drw15

tENS

Wx

WCLK

RCLK

REN

RT

OR

PAF

HF

PAE

Q0 - Qn

tSKEW4

12

1

tPAF

tHF

tPAE

tREF

Wx+1

2

W2

tENH

tRTS

WEN

tENS

W1

tENH

(4)

(5)

3

4

tENH

W3

tA

tA

NOTE:

1. X = 12 for the IDT72255LA and X = 13 for the IDT72265LA.

WCLK

SI

4670 drw 16

tENH

tENS

tLDS

tDS

BIT 0

EMPTY OFFSET

BIT X

BIT 0

FULL OFFSET

(1)

tENH

BIT X

(1)

tLDH

tLDH

tDH