IDT72255LA datasheet(2/28 Pages) RENESAS

2 / 28 page

IDT72255LA/72265LA CMOS SuperSync FIFO™

8,192 x 18 and 16,384 x 18

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

PIN CONFIGURATIONS

TQFP (PN64, ORDER CODE: PF)

STQFP (PP64, ORDER CODE: TF)

TOP VIEW

DESCRIPTION (CONTINUED)

PIN 1

WEN

SEN

VCC

GND

D17

D16

D15

D14

D13

D12

D11

D10

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Q17

Q16

GND

Q15

Q14

VCC

Q13

Q12

Q11

GND

Q10

GND

4670 drw02

SuperSync FIFOs are particularly appropriate for networking, video,

telecommunications,datacommunicationsandotherapplicationsthatneedto

bufferlargeamountsofdata.

TheinputportiscontrolledbyaWriteClock(WCLK)inputandaWriteEnable

(WEN)input. DataiswrittenintotheFIFOoneveryrisingedgeofWCLKwhen

WEN is asserted. The output port is controlled by a Read Clock (RCLK) input

andReadEnable(REN)input. DataisreadfromtheFIFOoneveryrisingedge

of RCLK when REN is asserted. An Output Enable (OE) input is provided for

three-statecontroloftheoutputs.

The frequencies of both the RCLK and the WCLK signals may vary from 0

tofMAXwithcompleteindependence.Therearenorestrictionsonthefrequency

of one clock input with respect to the other.

Therearetwopossibletimingmodesofoperationwiththesedevices:IDT

Standard mode and First Word Fall Through (FWFT) mode.

InIDTStandardmode,thefirstwordwrittentoanemptyFIFOwillnotappear

onthedataoutputlinesunlessaspecificreadoperationisperformed.Aread

operation,whichconsistsofactivatingRENandenablingarisingRCLKedge,

willshiftthewordfrominternalmemorytothedataoutputlines.

NOTE:

1. DC = Don’t Care. Must be tied to GND or VCC, cannot be left open.

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