SN250 datasheet(48/130 Pages) STMICROELECTRONICS

48 / 130 page

Functional description—application modules

SN250

48/130

EXP is written to the SC1_RATEEXP register and LIN to the SC1_RATELIN register. Since

the range for both values is 0 to 15, the fastest data rate is 12Mbps and the slowest rate is

22.9bps.

The SC1 SPI master supports various frame formats depending upon the clock polarity

(SC_SPIPOL), clock phase (SC_SPIPHA), and direction of data (SC_SPIORD) (see

Table 21). The register bits SC_SPIPOL, SC_SPIPHA, and SC_SPIORD are defined within

the SC1_SPICFG register.

Note:

Switching the SPI configuration from SC_SPIPOL=1 to SC_SPIPOL=0 without subsequently

setting SC1_MODE=0 and reinitializing the SPI will cause an extra byte (0xFE) to be

transmitted immediately before the first intended byte.

Serialized SC1 SPI transmit data is driven to the output pin MO. SC1 SPI master data is

received from the input pin MI. To generate slave select signals to SPI slave devices, other

GPIO pins have to be used and their assertion must be controlled by software.

Characters transmitted and received are passed through transmit and receive FIFOs. The

transmit and receive FIFOs are 4 bytes deep. These FIFOs are accessed under software

control by accessing the SC1_DATA data register or under hardware control using a DMA

controller.

Table 21.

SC1 SPI master frame format

SC1_SPICFG

Frame Format

210

SC1-3M

mode

210

SC1-3M

mode

210

SC1-3M

mode

210

SC1-3M

mode

211

SC1-3M

mode

Same as above except LSB first instead of MSB first

---

SC1-2

mode

Illegal

---

SC1-4A

mode

Illegal

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