SN250 datasheet(90/130 Pages) STMICROELECTRONICS

90 / 130 page

Functional description—application modules

SN250

90/130

Note:

All configuration changes do not take effect until the next edge of the timer’s clock source.

These functions are separately controlled for TMR1 and TMR2 by setting the bits TMR_CLK,

TMR_FILT

, TMR_EDGE, and TMR_PSCL in the timer registers TMR1_CFG and TMR2_CFG,

respectively.

7.4.2

Timer functionality (counting)

Each timer supports three counting modes: increasing, decreasing, or alternating (where

the counting will increase, then decrease, then increase). These modes are controlled by

setting the TMR_DOWN and TMR_BIDIR bits within the TMR1_CFG or TMR2_CFG registers.

Upward counting continues until the counter value reaches the threshold value stored in the

TMR1_TOP

or TMR2_TOP register. Downward counting continues until the counter value

reaches the value zero. When the alternating counting mode is enabled, a triangular-shaped

waveform of the count-value can be created. Figure 10 through Figure 13 illustrate the

different counting modes available from the timers.

Counting can be enabled and disabled with the register bit TMR_EN in the TMR1_CFG or

TMR2_CFG

registers. When the timer is disabled, the counter stops counting and maintains

its count value. Enabling can be masked with the pin TMR1ENMSK or TMR2ENMSK,

depending on register bit TMR_EXTEN in the TMR1_CFG or TMR2_CFG registers.

By default, the counting operation is repetitive. It can be restricted to single counting

enabled with the register bit TMR_1SHOT located in the TMR1_CFG or TMR2_CFG registers.

Table 28.

TMR1 and TMR2 clock source settings

TMR_CLK[1:0]

Clock Source

1 kHz RC clock

32.768kHz clock

12 MHz clock

GPIO clock input

Table 29.

Clock source divider settings

TMR_PSCL[3:0]

Clock Source Prescale Factor

N = 0..10

N = 11..15

210

Table 30.

Clock edge setting

TMR_EDGE

Clock Source

Rising

Falling

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