AD1986ABSTZ datasheet(33/56 Pages) AD

33 / 56 page

AD1986A

Rev. 0 | Page 33 of 56

Function

SPDIF configuration is supported. SPCV is always valid, independent of the SPDIF enable bit status.

SPCV

S/PDIF Configuration Status

Invalid SPDIF configuration (SPSA, SPSR, DAC slot rate, DRS)

(SPDIF

Configuration

Valid)

Valid SPDIF configuration

Actual status reflected in the CDAC (0x3A D06) bit.

PRI

CENTER DAC Power Status

Power on center DAC

Default

PRI

(Center DAC

Power-Down)

Power down center DAC

Actual status reflected in the SDAC bit.

PRJ

Surround DACs Power Control

Power on surround DACs

Default

PRJ

(Surround

DACs Power-

Down)

Power down surround DACs

Actual status reflected in the LDAC bit.

PRK

LFE DACs Power Control

Power on LFE DAC

Default

PRK

(LFE DAC

Power-Down)

Power down LFE DAC

Reserved.

Default: 0

FRONT DAC PCM RATE (REGISTER 0x2C)

This read/write sample rate control register contains 16-bit unsigned value, representing the rate of operation in Hz. If the VRA bit

(0x2A D00) is 0 this register is forced to 48 kHz (0xBB80). If VRA is 1, this register can be programmed with the actual sample rate.

To use 96 kHz in AC ’97 mode set the double rate audio (DRA) bit (0x2A D01). When using DRA in AC ’97, only the front DACs are

supported and all other DACs (surround, center, and LFE) are automatically powered down.

Reg

Name

D15

D14

D13

D12

D11

D10

Default

0x2C

Front DAC PCM

Rate

R15

R14

R13

R12

R11

R10

0xBB80

Table 92.

Function

R [15:0]

(Sample

Rate)

The sampling frequency range is from 7 kHz (0x01B58) to 48 kHz (0xBB80) in 1 Hz increments. If 0 is written to VRA, then the

sample rates are reset to 48 kHz.

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