DA7212 datasheet(57/136 Pages) RENESAS

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DA7212

Ultra-Low Power Stereo Codec

Datasheet

Revision 3.5

05-Jan-2022

CFR0011-120-00

57 of 135

S SLAVEaddr W

REG addr

SLAVEaddr

S = START condition

A = Acknowledge (low)

Sr = Repeated START condition

* = Not Acknowledge (NAK)

P = STOP condition

W = Write (low)

R = Read (high)

Master to Slave

7-bits

1-bit

8-bits

7-bits

DATA

1-bit

8-bits

SLAVEaddr

7-bits

DATA

1-bit

8-bits

Slave to Master

S SLAVEaddr W

REG addr

7-bits

1-bit

8-bits

Figure 23: Examples of the I2C byte read (SDA line)

Consecutive (Page Mode) read-out mode (CIF_I2C_WRITE_MODE (0x1D [0]) = 0) is initiated from

the master by sending an Acknowledge instead of Not Acknowledge (NAK) after receipt of the data

word. The I2C control block then increments the address pointer to the next I2C address and sends

the data to the master. This enables an unlimited read of data bytes until the master sends a NAK

directly after the receipt of data, followed by a subsequent STOP condition. If a non-existent I2C

address is read out, the DA7212 will return code zero.

S SLAVEaddr W A

REG addr

SLAVEaddr

S = START condition

A = Acknowledge (low)

Sr = Repeat START condition

* = Not Acknowledge (NAK)

P = STOP condition

W = Write (low)

R = Read (high)

Master to Slave

Slave to Master

7-bits

1 bit

8-bits

7-bits

DATA

1-bit

8-bits

S SLAVEaddr W

REG addr

SLAVEaddr

7-bits

1-bit

8-bits

7-bits

DATA

1-bit

8-bits

DATA

8-bits

Figure 24: Examples of I2C page read (SDA line)

The slave address after the Repeated START condition must be the same as the previous slave

address

Consecutive write-mode (CIF_I2C_WRITE_MODE (0x1D [0]) = 0) is supported if the master sends

several data bytes following a slave register address. The I2C control block then increments the

address pointer to the next I2C address, stores the received data and sends an acknowledge until

the master sends the STOP condition.

S SLAVEaddr W A

REGadr

DATA

S = START condition

A = Acknowledge (low)

Sr = Repeat START condition

* = Not Acknowledge (NAK)

P = STOP condition

W = Write (low)

R = Read (high)

Master to Slave

Slave to Master

7-bits

1 bit

8-bits

DATA

1-bit

8-bits

DATA

……….

8-bits

Repeated writes

Figure 25: I2C page write (SDA line)

An alternative repeated-write mode that uses non-consecutive slave register addresses is available

using the CIF_I2C_WRITE_MODE register. In this Repeat Mode (CIF_I2C_WRITE_MODE (0x1D

[0]) = 1), the slave can be configured to support a host’s repeated write operations into several non-

consecutive registers. Data is stored at the previously received register address. If a new START or

STOP condition occurs within a message, the bus returns to IDLE mode.

This is illustrated in Figure 26.

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