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DA7211 bảng dữ liệu(PDF) 65 Page - Renesas Technology Corp |
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DA7211 bảng dữ liệu(HTML) 65 Page - Renesas Technology Corp |
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65 / 111 page  DA7211 Ultra-low power stereo codec Datasheet Revision 3.2 23-Dec-2021 CFR0011-120-00 Rev 5 65 of 110 © 2021 Renesas Electronics 10 Register definitions WARNING: Any writes to RESERVED registers or bits can result in unexpected operation. This section gives an overview of all user accessible registers in the Register map table. Detailed descriptions are given in Register description tables, which are grouped per functional block. 10.1 Register map Table 38: Register map Address Function 7 6 5 4 3 2 1 0 Default 1 CONTROL WRITE_MODE NOISE_SUP BIAS_EN V_IO 0b00010000 2 STATUS MUTING SOFTMUTED I2S_LOCK PLL_LOCK 0b00000000 3 STARTUP1 SC_CLK_DIS SC_OVERRIDE SC_MST_EN 0b00000000 4 STARTUP2 0b00000000 5 STARTUP3 0b00000000 7 MIC_L MIC_L_EN MICBIAS_EN MIC_L_MUTE 0b00000000 8 MIC_R MIC_R_EN MIC_R_MUTE 0b00000000 9 AUX1_L AUX1_L_EN 0b00010000 0a AUX1_R AUX1_R_EN 0b00010000 0c IN_GAIN 0b00000000 0d INMIX_L IN_L_EN IN_L_OUTMIX_L IN_L_A1_L IN_L_MIC_R IN_L_MIC_L 0b00000000 0e INMIX_R IN_R_EN IN_R_IN_L N_R_OUTMIX_R IN_R_A1_R IN_L_MIC_L IN_L_MIC_R 0b00000000 0f ADC_HPF ADC_VOICE_EN ADC_HPF_EN 0b00001000 10 ADC ADC_R_EN ADC_R_MUTE ADC_L_EN ADC_L_MUTE ALC_EN 0b00000000 11 ADC_EQ1_2 0b00000000 12 ADC_EQ3_4 0b00000000 13 ADC_EQ5 ADC_EQ_EN 0b00000000 14 DAC_HPF DAC_VOICE_EN DAC_HPF_EN DAC_MUTE 0b00001000 15 DAC_L DAC_L_INV 0b00010000 16 DAC_R DAC_R_INV 0b00010000 17 DAC_SEL DAC_R_EN DAC_L_EN 0b01010100 18 SOFT_MUTE SOFT_MUTE RAMP_EN 0b01000000 19 DAC_EQ1_2 0b00000000 1a DAC_EQ3_4 0b00000000 1b DAC_EQ5 DAC_EQ_EN 0b00000000 1c OUTMIX_L OUT_L_EN OUT_L_INV OUT_L_DAC_L OUT_L_IN_R OUT_L_IN_L OUT_L_A1_L 0b00000000 1d OUTMIX_R OUT_R_EN OUT_R_INV OUT_R_DAC_R OUT_R_IN_R OUT_R_IN_L OUT_R_A1_R 0b00000000 1e OUT1_L OUT1_L_EN OUT1_L_SE 0b00110101 1f OUT1_R OUT1_R_EN OUT1_R_SE 0b00110101 21 HP_L_VOL 0b00010000 22 HP_R_VOL 0b00010000 23 HP_CFG HP_R_EN HP_MODE STEREO_TRACK HP_HIGHZ_R HP_L_EN HP_2CAP_MODE HP_HIGHZ_L 0b00000010 24 ZEROX HPZX_R_EN HPZX_L_EN OUTZX_R_EN OUTZX_L_EN INZX_R_EN INZX_L_EN A1ZX_R_EN A1ZX_L_EN 0b00000000 25 DAI_SRC_SEL DAI_IN_R_MIX DAI_IN_L_MIX 0b01110110 26 DAI_CFG1 DAI_MODE DAI_TDM_MONO 0b00000000 27 DAI_CFG2 0b00000000 28 DAI_CFG3 DAI_EN DAI_OE DAI_TDM 0b00001000 29 PLL_DIV1 0b00000000 2a PLL_DIV2 0b00000000 2b PLL_DIV3 PLL_BYP 0b00010000 2c PLL PLL_EN MCLK_SRM_EN MCLK_DET_EN MCLK_SHAPE_EN 0b00001010 2d GP1A_A0L 0b00000000 2e GP1A_A0H 0b01000000 2f GP1B_A0L 0b00000000 30 GP1B_A0H 0b01000000 31 GP2A_A0L 0b00000000 AUX1_R_VOL[5:0] STARTUP2[6:0] STARTUP3[6:0] MICBIAS_SEL[1:0] MIC_L_VOL[2:0] MIC_R_VOL[2:0] AUX1_L_VOL[5:0] ADC_EQ_GAIN[1:0] ADC_EQ5_VOL[3:0] INPGA_R_VOL[3:0] INPGA_L_VOL[3:0] ADC_VOICE_F0[2:0] ADC_HPF_F0[1:0] ADC_EQ2_VOL[7:4] ADC_EQ1_VOL[3:0] ADC_EQ4_VOL[7:4] ADC_EQ3_VOL[3:0] DAC_VOICE_F0[2:0] DAC_HPF_F0[1:0] DAC_L_GAIN[6:0] DAC_R_GAIN[6:0] DAC_R_SRC[2:0] DAC_L_SRC[2:0] DAC_EQ_GAIN DAC_EQ5_VOL[3:0] OUT1_L_VOL[5:0] OUT1_R_VOL[5:0] MUTE_RATE[2:0] DAC_EQ2_VOL[7:4] DAC_EQ1_VOL[3:0] DAC_EQ4_VOL[7:4] DAC_EQ3_VOL[3:0] HP_L_VOL[5:0] HP_R_VOL[5:0] DAI_OUT_R_SRC[2:0] DAI_OUT_L_SRC[2:0] DAI_FRAME[1:0] DAI_WORD[1:0] GP2A_A0L[7:0] DAI_TDM_OFFS[7:0] DAI_FORMAT[1:0] PLL_DIV_H[7:0] PLL_DIV_M[7:0] MCLK_RANGE[1:0] PLL_DIV_L[3:0] FS[3:0] GP1A_A0L[7:0] GP1A_A0H[7:0] GP1B_A0L[7:0] GP1B_A0H[7:0] |
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