RA4E2 datasheet(51/90 Pages) RENESAS

51 / 90 page

Note:

tI3Ccyc: I3C internal reference clock (I3Cφ) cycle, tTcyc: I3CCLK cycle.

Note:

Values in parentheses apply when INCTL.DNFS[3:0] is set to 0x3 while the digital filter is enabled with INCTL.DNFE set to 1.

Note:

Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the IIC

interface, the AC portion of the electrical characteristics is measured for each group.

Note 1. Cb indicates the total capacity of the bus line.

Table 2.29

IIC timing(1)-2

1. Conditions: Middle drive output is selected in the Port Drive Capability bit in the PmnPFS register for the following pins: SDA0_A,

SCL0_A, SDA0_B, SCL0_B, SDA0_C, SCL0_C.

2. The following pins do not require setting: SDA0_D, SCL0_D.

3. Use pins that have a letter appended to their names, for instance “_A” or “_B”, to indicate group membership. For the IIC interface, the

AC portion of the electrical characteristics is measured for each group.

Parameter

Symbol

Min

Max

Unit

IIC

(Fast-mode)

SCL input cycle time

tSCL

10(18) × tI3Ccyc + 600

—

SCL input high pulse width

tSCLH

5(9) × tI3Ccyc + 300

—

SCL input low pulse width

tSCLL

5(9) × tI3Ccyc + 300

—

SCL, SDA rise time

tSr

20 × (external pullup

voltage/5.5 V)*1

300

SCL, SDA fall time

tSf

20 × (external pullup

voltage/5.5 V)*1

300

SCL, SDA input spike pulse removal

time

tSP

1(4) × tI3Ccyc

SDA input bus free time when wakeup

function is disabled

tBUF

5(9) × tI3Ccyc + 300

—

SDA input bus free time when wakeup

function is enabled

tBUF

5(9) × tI3Ccyc + 4 × tTcyc + 300 —

START condition input hold time when

wakeup function is disabled

tSTAH

tI3Ccyc + 300

—

START condition input hold time when

wakeup function is enabled

tSTAH

1(5) × tI3Ccyc + tTcyc + 300

—

Repeated START condition input setup

time

tSTAS

300

—

STOP condition input setup time

tSTOS

300

—

Data input setup time

tSDAS

tI3Ccyc + 50

—

Data input hold time

tSDAH

—

SCL, SDA capacitive load

Cb*2

—

400

Note:

tI3Ccyc: I3C internal reference clock (I3Cφ) cycle, tTcyc: I3CCLK cycle.

Note:

Values in parentheses apply when INCTL.DNFS[3:0] is set to 0x3 while the digital filter is enabled with INCTL.DNFE set to 1.

Note:

Must use pins that have a letter appended to their name, for instance “_A”, “_B”, to indicate group membership. For the IIC

interface, the AC portion of the electrical characteristics is measured for each group.

Note 1. Only supported for SDA0_D, SCL0_D.

Note 2. Cb indicates the total capacity of the bus line.

RA4E2 Datasheet

2. Electrical Characteristics

R01DS0413EJ0110 Rev.1.10

Feb 28, 2023

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