P9242-R Datasheet

© 2018 Integrated Device Technology, Inc

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January 16, 2018

8.2 Bit Decoding Scheme for ASK

As required by the WPC, the P9242-R uses a differential bi-phase coding scheme to demodulate data bits onto the power signal. A clock

frequency of 2kHz is used for this purpose. A logic ONE bit is coded using two narrow transitions, whereas a logic ZERO bit is encoded using

one wider transition as shown below:

Figure 20. Bit Decoding Scheme

tCLK

ONE

ZERO

ONE

ZERO

ONE

ONE

ZERO

ZERO

8.3 Byte Decoding for ASK

Each byte in the communication packet comprises 11 bits in an asynchronous serial format, as shown in Figure 21.

Figure 21. Byte Decoding Scheme

Start

Stop

Parity

b01

2

3

4

5

6

7

b

bbbb

b

b

Each byte has a start bit, 8 data bits, a parity bit, and a single stop bit.

8.4 Packet Structure

The P9242-R communicates with the base station via communication packets. Each communication packet has the following structure:

Figure 22. Communication Packet Structure

Preamble

Header

Message

Checksum