L9969X datasheet(40/70 Pages) STMICROELECTRONICS

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3.2.7

SPI Interface

3.2.7.1

SPI general description

The SPI interface establishes a communication between the H-bridge and the systems microcontroller. The

H-bridge is always operated in the slave mode whereas the microcontroller provides the master functions.

By applying an active slave select signal at NSS, the H-bridge is selected by the SPI master. SI is the data input

(Slave In), SO the data output (Slave Out). Via SCK (Serial Clock Input), the SPI clock is provided by the SPI

master.

In case of inactive slave select signal (high), the data output SO is in high impedance state (tristate).

Depending on the application, the first two bits of an instruction may be used to establish an extended device-

addressing. Doing this, one common NSS channel may be shared by up to 4 Slave-devices.

Thresholds are independent from VDD and defined in a way to be compatible to 3.3 V and 5.0 V ports, if VDD is

in its operational range.

In absence of VS, the full functionality of the SPI-interface is still given.

Figure 27. SPI block diagram

For twin version, since there are two NSS pins competing for the data lines, they must not be asserted

simultaneously. In the event that this occurs, the data lines will be managed as shown in the figure below:

L9969x

Functional behavior in detail

DS14029 - Rev 3

page 40/70

L9969X bảng dữ liệu(PDF) 40 Page - STMicroelectronics