6.3.3

Current sense input

The power switch current is read across a shunt resistor placed between the source of the switch and ground.

Said voltage is compared with the value generated by the THD optimizer.

The leading edge blanking (LEB) unit prevents the turn-on spikes from reaching the PWM comparator and avoids

false triggering.

When the primary side regulation (PSR) loop serves very light loads, the demagnetization time is very short, and

the PSR sampling unit could underestimate the output voltage and could react increasing the real voltage. In

order to guarantee a correct sampling of VOUT, a minimum current sense level is activated when PSR burst-mode

is active.

The propagation delay of the peak current detection to GD off (TPD + external TPROP) results in a turn-off current

that is higher than expected. Said error is proportional to input voltage.

The HVLED101 embeds a propagation delay compensation logic that injects a portion of the current sourced by

ZCD pin during on-time into the CS pin. Said current multiplied by the resistance that is placed between CS pin

and the shunt resistor develops a voltage offset that compensates the above mentioned error.

Vcs.OS= RFFRZCD∙KFF∙NauxNpri∙VIN=RCS∙ TPD+TPROP

LP ∙VIN

Since RZCD must be fixed at first to have proper biasing of ZCD pin, then RFF can be used to adjust the

propagation delay compensation.

6.3.4

Feedback inputs

6.3.4.1

OPTO

The OPTO pin is intended to bias and manage the signal coming from the phototransistor collector of a standard

optocoupler operating as pull-down current generator.

An internal degeneration resistor facilitates the loop compensation equalizing the ideal current source that bias

the pin.

When OPTO pin voltage is lower than burst-mode threshold, the IC stops switching and enters deep low

consumption mode: this mechanism can be used also as an alternate entry to disable the IC.

6.3.4.2

FB

The FB pin is internally connected to the output of the PSR error amplifier: the PSR loop compensation network

must be placed between this pin and GND

When FB pin voltage is lower than PSR burst-mode threshold, the IC starts to generate the PSR burst-mode

algorithm, described into the relevant paragraph.

The voltage of the FB pin is internally applied to a “MIN selection” structure together with OPTO pin voltage and

MCP internal signal (see “Maximum power control” section).

In order to improve PSR performance, FB is put in high impedance state when input voltage is near zero crossing.

6.3.5

Zero Current Detection (ZCD)

The ZCD pin is intended to realize the zero current detection mechanism according to the state diagram of

Figure 10.

6.3.5.1

ZCD state machine description

When the MOSFET turns off, the HVLED101 applies a minimum blanking time (TBLANK) in order to reject spurious

oscillations.

Said blanking time is longer when VOUT is lower than the undervoltage protection level: in fact, huge oscillations

are foreseen in case of output short-circuit.

After minimum blanking time, ZCD logic checks the level of ZCD voltage, if it is higher than arming threshold, then

it waits indefinitely for the first falling edge on the ZCD pin below the triggering threshold.

On the contrary, if ZCD level is lower than the arming threshold, a maximum waiting time (TWAIT) is started to

prevent latching conditions.

Said waiting time (TWAIT) is proportional to the programmed delay time (TDLY) configured by RDLY resistor on

DLY/CFG pin as per the following relationship:

TWAIT=8∙ TDLY−100ns +100ns

HVLED101

Control loop

DS14143 - Rev 2

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