6.3.1

Multiplier and THD optimization

The HVLED101 is primarily intended to deliver power to a load from an AC line. A multiplier is needed to shape

the current sense threshold and obtain the desired power factor correction.

The proprietary THD optimizer embedded into HVLED101 minimizes the distortion of the absorbed AC current

(THD) and maximizes the Power Factor (PF), independently from the particular set-up of the transformer (turn

ratio and primary inductance).

The THD optimization unit is placed between the multiplier output and the current sense threshold limiter and is

active during active mode only.

The IC performance is optimized for the use of a transformer that has a reflected voltage (Vout times turn ratio)

into a range between 100 V and 250 V.

The current sense threshold is given by the following relationship:

VCS= VHVSU

VHVSU_pk∙ KMδTHDθ ∙ VFBint−VOS

Figure 8. Multiplier and THD optimizer block diagram

VMULT

CTHD

VPK

Vmult,norm

FB

OPTO

MIN

(FB, OPTO)

VFBint

VOS

-

+

VCS-TH

V to I

converter

HVSU

ACTIVE MODE

1/X

KMPC-X

MPC

Fc = 10kHz

K_hv_CFG

GD

RTHD

MIN

(FBint, MPC)

THD

Where KM is the DC gain of the THD optimizer and δTHD(θ) is the duty cycle of the internal optimizer MOSFET.

An external Capacitor, CTHD, connected between THD pin and GND is used to filter the switching frequency from

VCS threshold. The value of such capacitor must be selected in order to obtain:

τTHD=RTHD∙CTHD= 3to5 ∙ 1FSW_min

The internal THD switch is normally switched together with GD: if valley skipping operation is running, the THD

pin is put in high impedance on in correspondence with the 6th valid falling edge of ZCD signal.

The THD MOSFET activity is described in Table 7.

The minimum value of VCS is set to VCS-RU during startup or VCS-MIN when PSR burst-mode is activated, while it

is zero during normal operation.

The peak detector of the input voltage divider is intended to operate when the peak amplitude (or DC value) of the

input voltage is between 105 V and 480 V (CFG1, CFG2 or CFG5) or between 175 V and 760 V (CFG3 or CFG4).

HVLED101

Control loop

DS14143 - Rev 2

page 16/36