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ST25R3920 bảng dữ liệu(PDF) 49 Page - STMicroelectronics

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ST25R3920 bảng dữ liệu(HTML) 49 Page - STMicroelectronics

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DS13261 Rev 9
49/152
ST25R3920
Application information
151
Figure 13. SPI communication: reading a single byte
Read or write access to register space-B
To access the register space-B the register read or write SPI sequence has to be prefixed
with the byte FBh. Access to register space-B remains active until the rising edge of BSS.
Loading transmitting data into FIFO
Loading the transmitting data into the FIFO is similar to writing data into an addressable
registers. The SPI sequence starts with SPI operation mode bits ‘10’ to indicate a FIFO
operation followed by bits <C5:C0> set to 000000b. After the FIFO mode byte at least one
and up to 512 data bytes must be sent.
Figure 14 shows how to load the transmitting data into the FIFO.
Figure 14. SPI communication: FIFO loading
MS51646V1
SCLK rising edge
Data transferred from MCU
SCLK falling edge
Data is sampled
BSS raising
edge indicates
end of
Read mode
Two leading bits
indicate Mode
BSS
SCLK
MOSI
0
1
A5
A4
A3
A2
A1
A0
X
X
D4
D3
D2
D1
D0
D7
D6
tristate
tristate
D5
MISO
SCLK rising edge
Data moved from
Address A5-A0
SCLK falling edge
Data transferred to MCU
MS51647V1
SCLK rising edge
Data transferred from MCU
SCLK falling edge
Data is sampled
BSS
raising edge
indicates end
of FIFO mode
1
000
0
0
0
0
X
X
BSS
SCLK
MOSI
10 pattern
indicates
FIFO mode
1 to 512
bytes
Start of
paylod data



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