STM32G0C1NET3 datasheet(16/159 Pages) STMICROELECTRONICS

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Functional overview

STM32G0C1xC/xE

16/159

DS13564 Rev 4

3.4

Embedded SRAM

STM32G0C1xC/xE devices have 128 Kbytes of embedded SRAM with parity. Hardware

parity check allows memory data errors to be detected, which contributes to increasing

functional safety of applications.

When the parity protection is not required because the application is not safety-critical, the

parity memory bits can be used as additional SRAM, to increase its total size to 144 Kbytes.

The memory can be read/write-accessed at CPU clock speed, with 0 wait states.

3.5

Boot modes

At startup, the boot pin and boot selector option bit are used to select one of the three boot

options:

•

boot from User Flash memory

•

boot from System memory

•

boot from embedded SRAM

The boot pin is shared with a standard GPIO and can be enabled through the boot selector

option bit. The boot loader is located in System memory. It manages the Flash memory

reprogramming through one of the following interfaces:

•

USART on pins PA9/PA10, PC10/PC11, or PA2/PA3

•

I2C-bus on pins PB6/PB7 or PB10/PB11

•

SPI on pins PA4/PA5/PA6/PA7 or PB12/PB13/PB14/PB15

•

FDCAN on pins PD0/PD1

3.6

Cyclic redundancy check calculation unit (CRC)

The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a

configurable generator polynomial value and size.

Among other applications, CRC-based techniques are used to verify data transmission or

storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of

verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of

the software during runtime, to be compared with a reference signature generated at link

time and stored at a given memory location.

•

USB on pins PA11/PA12

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