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STM32U5A5QJ bảng dữ liệu(PDF) 62 Page - STMicroelectronics

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Giải thích chi tiết về linh kiện  Ultra-low-power Arm® Cortex®-M33 32-bit MCUTrustZone®FPU,240 DMIPS, 4 MB Flash, 2.5 MB SRAM, LTDC, MIPI® DSI, crypto
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nhà sản xuất  STMICROELECTRONICS [STMicroelectronics]
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STM32U5A5QJ bảng dữ liệu(HTML) 62 Page - STMicroelectronics

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Functional overview
STM32U5Axxx
62/382
DS13543 Rev 1
The main features of the FSMC are the following:
•
Interface with static-memory mapped devices including:
–
Static random access memory (SRAM)
–
NOR flash memory/OneNAND flash memory
–
PSRAM (four memory banks)
–
NAND flash memory with ECC hardware to check up to 8 Kbytes of data
–
Ferroelectric RAM (FRAM)
•
8-,16- bit data bus width
•
Independent chip select control for each memory bank
•
Independent configuration for each memory bank
•
Write FIFO
3.26.1
LCD parallel interface
The FSMC can be configured to interface seamlessly with most graphic LCD controllers. It
supports the Intel® 8080 and Motorola® 6800 modes, and is flexible enough to adapt to
specific LCD interfaces.
This LCD parallel interface capability makes it easy to build cost effective graphic
applications using LCD modules with embedded controllers or high-performance solutions
using external controllers with dedicated acceleration.
3.26.2
FSMC TrustZone security
When the TrustZone security is enabled, the whole FSMC banks are secure after reset.
Nonsecure area can be configured using the TZSC MPCWMx controller:
•
FSMC NOR/PSRAM bank:
–
Up to two nonsecure area can be configured thought the TZSC MPCWM2
controller with a 64-Kbyte granularity
•
FSMC NAND bank:
–
Can be either configured as fully secure or fully nonsecure using the TZSC
MPCWM3 controller
The FSMC registers can be configured as secure through the TZSC controller.
3.27
Octo-SPI interface (OCTOSPI)
The devices embed two OCTOSPIs. The OCTOSPI supports most external serial memories
such as serial PSRAMs, serial NAND and serial NOR Flash memories, HyperRAMs™ and
HyperFlash™ memories, with the following functional modes:
•
Indirect mode: all the operations are performed using the OCTOSPI registers.
•
Status-polling mode: the external memory status register is periodically read and
an interrupt can be generated in case of flag setting.
•
Memory-mapped mode: the external memory is memory mapped and is seen by the
system as if it were an internal memory supporting read and write operation.



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