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STM32H7B3AI bảng dữ liệu(PDF) 178 Page - STMicroelectronics

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Table 121. MDIO Slave timing parameters
Symbol
Parameter
Min
Typ
Max(1)
Unit
FMDC
Management Data Clock
-
-
30
MHz
td(MDIO)
Management Data Iput/output output valid time
9
11
21
ns
tsu(MDIO)
Management Data Iput/output setup time
2.5
-
-
th(MDIO)
Management Data Iput/output hold time
1
-
-
1. At VOS1, these values are degraded by up to 5 %.
Figure 75. MDIO Slave timing diagram
tsu(MDIO)
tMDC)
th(MDIO)
td(MDIO)
6.3.36.7
SD/SDIO MMC card host interface (SDMMC) characteristics
Unless otherwise specified, the parameters given in Table 122 and Table 123 for SDIO are derived from
tests performed under the ambient temperature, fPCLKx frequency and VDD supply voltage summarized in
Table 22. General operating conditions and Section 6.3.1 , with the following configuration:
•
Output speed is set to OSPEEDRy[1:0] = 11
•
Capacitive load CL=30 pF
•
Measurement points are done at CMOS levels: 0.5VDD
•
IO Compensation cell activated.
•
HSLV activated when VDD ≤ 2.7 V
•
VOS level set to VOS0
Note:
At VOS1, the performance can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote
when applicable.
Refer to Section 6.3.16 I/O port characteristics for more details on the input/output characteristics.
Table 122. Dynamics characteristics: SDMMC characteristics, VDD=2.7 to 3.6 V
Above 100 MHz, CL = 20 pF.
Symbol
Parameter
Conditions
Min(1)
Typ(1)
Max(1)(2)
Unit
fPP
Clock frequency in data transfer mode
-
0
-
133
MHz
-
SDIO_CK/fPCLK2 frequency ratio
-
-
-
8/3
-
tW(CKL)
Clock low time
fPP =52 MHz
8.5
9.5
-
ns
tW(CKH)
Clock high time
fPP =52 MHz
8.5
9.5
-
CMD, D inputs (referenced to CK) in eMMC legacy/SDR/DDR and SD HS/SDR/DDR mode
STM32H7B3xI
Operating conditions
DS13139 - Rev 8
page 178/238



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