STM32H7B3AI datasheet(176/238 Pages) STMICROELECTRONICS

176 / 238 page

6.3.36.5

SAI characteristics

Unless otherwise specified, the parameters given in Table 120 for SAI are derived from tests performed under

the ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 22. General

operating conditions and Section 6.3.1 , with the following configuration:

•

Output speed is set to OSPEEDRy[1:0] = 10

•

Capacitive load CL = 30 pF

•

IO Compensation cell activated.

•

Measurement points are done at CMOS levels: 0.5VDD

•

VOS level set to VOS0

Note:

At VOS1, the performance can be degraded by up to 5 % compared to VOS0. This is indicated by a footnote

when applicable.

Refer to Section 6.3.16 I/O port characteristics for more details on the input/output alternate function

characteristics (SCK,SD,WS).

Table 120. SAI characteristics

Symbol

Parameter

Conditions

Min(1) Max(1)(2) Unit

fMCK

SAI Main clock output

MHz

fCK

SAI clock frequency

Master transmitter, 2.7 ≤ VDD ≤ 3.6 V

Master transmitter, 1.62 ≤ VDD ≤ 3.6 V

Master receiver, 1.6 ≤ VDD ≤ 3.6 V

Slave transmitter, 2.7 ≤ VDD ≤ 3.6 V

Slave transmitter, 1.62 ≤ VDD ≤ 3.6 V

Slave receiver, 1.62 ≤ VDD≤ 3.6 V

tv(FS)

FS valid time

Master mode,2.7 ≤ VDD ≤ 3.6 V

14.5

Master mode, 1.62 ≤ VDD ≤ 3.6 V

18.5

tsu(FS)

FS setup time

Slave mode

th(FS)

FS hold time

Master mode

FS hold time

Slave mode

tsu(SD_A_MR)

Data input setup time

Master receiver

0.5

tsu(SD_B_SR)

Slave receiver

th(SD_A_MR)

Data input hold time

Master receiver

5.5

th(SD_B_SR)

Slave receiver

tv(SD_B_ST)

Data output valid time

Slave transmitter (after enable edge), 2.7 ≤ VDD ≤ 3.6 V

13.5

Slave transmitter (after enable edge), 1.62 ≤ VDD ≤ 3.6 V

16.5

th(SD_B_ST)

Data output hold time

Slave transmitter (after enable edge)

tv(SD_A_MT)

Data output valid time

Master transmitter (after enable edge), 2.7 ≤ VDD ≤ 3.6 V

Master transmitter (after enable edge), 1.62 ≤ VDD ≤ 3.6 V

th(SD_A_MT)

Data output hold time

Master transmitter (after enable edge)

7.5

1. Guaranteed by characterization results.

2. At VOS1, these values are degraded by up to 5 %.

3. APB clock frequency must be at least twice SAI clock frequency.

STM32H7B3xI

Operating conditions

DS13139 - Rev 8

page 176/238

STM32H7B3AI bảng dữ liệu(PDF) 176 Page - STMicroelectronics

STM32H7B3AI bảng dữ liệu(HTML) 176 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

bảng dữ liệu tải về

Link URL