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18

Revision 2.2

2.2.6

Audio In Interface Signals

Signal Name

Ball

No.

Type

Description

AI_OSCLK

B15

O

Over-Sampling Clock. This output can be programmed to emit any fre-

quency up to 40 MHz with a sub-Hertz resolution. It is intended for use

board level 27 to 33

Ω series resistor is recommended to reduce ringing.

AI_SCK

A16

I/O

Serial Clock. When the AI module is programmed as a serial-interface

timing slave (power-up default), AI_SCK is an input. AI_SCK receives

the serial bit clock from the external A/D subsystem. This clock is treated

as fully asynchronous to the CS1301/CS1311 main clock.

When the AI module is programmed as the serial-interface timing mas-

ter, AI_SCK is an output. AI_SCK drives the serial clock for the external

A/D subsystem. The frequency is a programmable integral divisor of the

AI_OSCLK frequency.

AI_SCK is limited to 22 MHz. The sample rate of valid samples embed-

ded within the serial stream is variable. If used as an output, a board

level27to33

Ω series resistor is recommended to reduce ringing.

AI_SD

C15

I

Serial Data. Serial data from external A/D subsystem. Data on this pin is

sampled on positive or negative edges of AI_SCK as determined by the

CLOCK_EDGE bit in the AI_SERIAL register.

AI_WS

B16

I/O

Word-Select. AI_WS is the word-select or frame-synchronization signal

from/to the external A/D subsystem.

When the AI module is programmed as the serial-interface timing slave

(power-up default), AI_WS acts as an input. AI_WS is sampled on the

same edge as selected for AI_SD.

When the AI module is programmed as the serial-interface timing mas-

ter, AI_WS acts as an output. It is asserted on the opposite edge of the

AI_SD sampling edge.

Note:

The AI module always acts as receiver, but can be master or slave for A/D timing.

Video In and Audio In are supported by third party software solutions, not by the National solution.