M5CAARCH-RMSLASHD datasheet(74/114 Pages) NXP

tên linh kiện	M5CAARCH-RM/D

Giải thích chi tiết về linh kiện	C-3e Network Processor Silicon Revision A1

PDF	114 Pages

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CHAPTER 3: ELECTRICAL SPECIFICATIONS

C3EN

Power Sequencing

It is intended that the VDD33/VDDT and VDD rails are sequenced to their final value

together for most applications. VDD33 and VDDT must be above VDD at all times. VDD

must be brought to its final value within 100ms of sequencing on VDD33 and VDDT.

It is also required that SCLK, SCLKX, TCLKI, PCLK, MDCLK, FTXCLK, and FRXCLK be running

or begin running during power sequencing to propagate reset inside the C-3e NP. Figure 9

indicates the relationship between the clocks and PRSTX. There is no requirement that the

asserting and deasserting edges of PRSTX be synchronous to the clocks. Reset must be

asserted within 100

µs of power initiation. Typically, reset is held low during power

initiation.

Figure 9 Bringup Clock Timing Diagram

TCLKI, PCLK,

SCLK, SCLKX,

MDCLK, FTXCLK,

FRXCLK

PRSTX

³1ms

³100

µs

(

)

≤100

µs

VDD, VDD33,

VDDT

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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