M5CAARCH-RMSLASHD datasheet(25/114 Pages) NXP

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Table Lookup Unit

Some of these parameters are programmed into the SDRAMs’ mode register and can be

applied only once per power cycle. The ECC functionality can be enabled or disabled via

configuration register writes.

If needed, the interface can narrowed to 128bits by disabling ECC and providing board

pull-ups for the two control bits and nine ECC bits. This is useful if DIMMs are used in the

board design. If individual SDRAM parts are used, x16 and x32 are supported. The BMU

supports SDRAM devices that use 12 address lines. Internal address calculation paths limit

the maximum memory size to 128MBytes. Only one physical bank of SDRAM is supported.

Table Lookup Unit

The Table Lookup Unit (TLU) performs table lookups in external SRAM. It can also be used

for statistics accumulation and retrieval and as general data storage. The TLU

simultaneously supports multiple application-defined tables and multiple search

strategies, such as those needed for routing, circuit switching, and QoS lookup tasks.

The C-3e NP uses external 64bit wide ZBT Pipelined Bursting Static RAM (SRAM) modules

(at frequencies up to 125MHz) for storage of its tables. These modules allow

implementation of tables with 225 x 64bit entries using 8Mbit SRAM technology. The

maximum amount of memory supported by the TLU is 128MBytes in four banks, when

SRAM technology supports 4M x 18pins parts.

Table 5 TLU SRAM Configurations

SRAM TECHNOLOGY

MIN TABLE SIZE

(ONE BANK)

MAXIMUM TABLE SIZE

(FOUR BANKS)

1Mbit (32k x 32pins)

256kBytes

1MBytes

2Mbit (64k x 32pins)

512kBytes

2MBytes

4Mbit (256k x 18pins)

2MBytes

8MBytes

8Mbit (512k x 18pins)

4MBytes

16MBytes

16Mbit (1M x 18pins)

8MBytes

32MBytes

32Mbit (2M x 18pins)

16MBytes

64MBytes

64Mbit (4M x 18pins)

32MBytes

128MBytes

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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