HC705RC16GRSSLASHD datasheet(71/120 Pages) NXP

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Carrier Modulator Transmitter (CMT)

Carrier Generator

MC68HC705RC16 — Rev. 3.0

General Release Specification

Carrier Modulator Transmitter (CMT)

PH0–PH5 and PL0–PL5 — Primary Carrier High and Low Time Data

Values

When selected, these bits contain the number of input clocks required

to generate the carrier high and low time periods. When operating in

time mode (see 9.5.1 Time Mode), this register pair is always

selected. When operating in FSK mode (see 9.5.2 FSK Mode), this

under control of the modulator. The primary carrier high and low time

values are undefined out of reset. These bits must be written to

non-zero values before the carrier generator is enabled to avoid

spurious results.

NOTE:

Writing to CHR1 to update PH0–PH5 or to CLR1 to update PL0–PL5 will

also update the IRO latch. When MCGEN (bit 0 in the MCSR) is clear,

the IRO latch value appears on the IRO output pin. Care should be taken

that bit 7 of the data to be written to CHR1 or CHL1 should contain the

desired state of the IRO latch.

SH0–SH5 and SL0–SL5 — Secondary Carrier High and Low Time Data

Values

When selected, these bits contain the number of input clocks required

to generate the carrier high and low time periods. When operating in

time mode (see 9.5.1 Time Mode), this register pair is never selected.

When operating in FSK mode (see 9.5.2 FSK Mode), this register pair

and the secondary register pair are alternately selected under control

Address:

$0013

Bit 7

654321

Bit 0

Read:

SL5

SL4

SL3

SL2

SL1

SL0

Write:

Reset:

UUUUUU

U = Unaffected

Figure 9-6. Carrier Generator Data Register CLR2

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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