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HC05V7GRS/D bảng dữ liệu(PDF) 106 Page - NXP Semiconductors

tên linh kiện HC05V7GRS/D
Giải thích chi tiết về linh kiện  Low cost, HC05 Core
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SECTION 15: MESSAGE DATA LINK CONTROLLER
Page 92
MC68HC05V7 Specification Rev. 1.0
15.1
OUTLINE
The CPU Interface contains the software addressable registers and provides the link
between the CPU and the Tx and Rx Buffers. The Tx and Rx Buffers provide storage for
data received and data to be transmitted onto the J1850 bus. The Protocol Handler is
responsible for the encoding and decoding of data bits and special message symbols
during transmission and reception. The MUX Interface provides the link between the MDLC
digital section and the analog Physical Interface. The wave shaping, driving, and digitizing
of data is performed by the Physical Interface.
NOTE:
The bus data rate depends upon the microcontroller oscillator frequency
(f
OSC) and the MDLC rate selection control bits (R0, R1). The correct
combination for the application must be chosen in order for J1850 bus
communications to take place. See 15.2.2.3 R1, R0 - Rate Select.
Physical Interface
To CPU
Protocol Handler
MUX Interface
CPU Interface
Rx/Tx
Buffers
To J1850 Bus
MDLC
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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