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HC05V7GRS/D bảng dữ liệu(PDF) 44 Page - NXP Semiconductors

tên linh kiện HC05V7GRS/D
Giải thích chi tiết về linh kiện  Low cost, HC05 Core
PDF  170 Pages
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nhà sản xuất  NXP [NXP Semiconductors]
Trang chủ  http://www.nxp.com
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HC05V7GRS/D bảng dữ liệu(HTML) 44 Page - NXP Semiconductors

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SECTION 5: INTERRUPTS
Page 30
MC68HC05V7 Specification Rev. 1.0
The M68HC05 CPU does not support interruptible instructions, therefore, the maximum
latency to the first instruction of the interrupt service routine must include the longest
instruction execution time plus stacking overhead.
Latency = (Longest instruction execution time + 10) x tCYC secs
An RTI instruction is used to signify when the interrupt software service routine is
completed. The RTI instruction causes the register contents to be recovered from the stack
and normal processing to resume at the next instruction that was to be executed when the
interrupt took place. Figure 5-1 shows the sequence of events that occur during interrupt
processing.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com



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