DFE252012P-2R2M datasheet(18/44 Pages) MICROCHIP

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MCP16501

DS20006388A-page 18

 2020 Microchip Technology Inc.

4.3.4

PWRHLD, LPM, LEN AND POWER

STATES DEFINITIONS

PWRHLD and LPM define different power states which

are illustrated in Table 4-2. These are default definitions

for the MCP16501A. Other default definitions are possi-

ble for different or customized product variants.

The LDO operation is completely independent of the

power states and is controlled by the LEN pin. The only

exception to this is in the case of MCP16501D, used in

LPDDR2 applications where the LDO is used to power

the memory alongside Buck2. For more details on this

see Section 5.3, LPDDR2 Support with Hibernate

Mode-MCP16501D Only.

Other logic combinations of PWRHLD and LPM are for-

bidden. The initial state is the OFF state (shutdown).

The process by which the MCP16501 abandons the

OFF state and enters the other possible power states is

defined as the power-up sequence, which is described

in Section 4.4.1 “Typical Power-up Sequence and

Timing”. The following state diagram in Figure 4-2 illus-

trates the power states of MCP16501 and their typical

and/or permissible dynamic transitions.

FIGURE 4-2:

Finite State Machine (FSM) States Diagram for MCP16501.

TABLE 4-2:

DEFAULT POWER STATES DEFINITION (MCP16501A)

PWRHLD

LPM

Buck1

Buck2

Buck3

LDO

nRSTO

Power State

Off

LEN Controlled Low

Off

Auto-PFM

Off

LEN Controlled Low

Hibernate

mode

Auto-PFM

LEN Controlled High-Z

Low-Power

mode

FPWM

LEN Controlled High-Z

Active mode

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