• Keep the FB trace as short as possible by placing the feedback resistors close to the FB pin. Reduce noise

sensitivity of the output voltage feedback path by placing the resistor divider close to the FB pin, rather than

close to the load. FB is the input to the voltage-loop error anplifier and represents a high-impedance node

sensitive to noise. Route a trace from the upper feedback resistor to the required point of output voltage

regulation.

• Use a solid ground plane on the PCB layer directly below the top layer with the module. This plane acts as

a noise shield by minimizing the magnetic fields associated with the currents in the switching loops. Connect

AGND pins 6 and 11 directly to PGND pin 19 under the module.

• Provide enough PCB area for proper heatsinking. Use sufficient copper area to acheive a low thermal

impedance commensurate with the maximum load current and ambient temperature conditions. Provide

adequate heatsinking for the TLVM13610 to keep the junction temperature below 150°C. For operation at

full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of heat-sinking

vias to connect the exposed pads (PGND) of the package to the PCB ground plane. If the PCB has multiple

copper layers, connect these thermal vias to inner-layer ground planes. Make the top and bottom PCB layers

preferably with two-ounce copper thickness (and no less than one ounce).

9.4.1.1 Thermal Design and Layout

For a DC/DC module to be useful over a particular temperature range, the package must allow for the efficient

removal of the heat produced while keeping the junction temperature within rated limits. The TLVM13610

module is available in a small 6.5-mm × 7.55-mm 22-pin QFN (RDL) package to cover a range of application

requirements. The Thermal Information table summarizes the thermal metrics of this package with related detail

provided by the Semiconductor and IC Package Thermal Metrics application report.

The 22-pin QFN package offers a means of removing heat through the exposed thermal pads at the base of

the package. This allows a significant improvement in heatsinking, and it becomes imperative that the PCB

is designed with thermal lands, thermal vias, and one or more ground planes to complete the heat removal

subsystem. The exposed pads of the TLVM13610 are soldered to the ground-connected copper lands on the

PCB directly underneath the device package, reducing the thermal resistance to a very low value.

Preferably, use a four-layer board with 2-oz copper thickness for all layers to provide low impedance, proper

shielding and lower thermal resistance. Numerous vias with a 0.3-mm diameter connected from the thermal

lands to the internal and solder-side ground planes are vital to promote heat transfer. In a multi-layer PCB

stack-up, a solid ground plane is typically placed on the PCB layer below the power-stage components. Not only

does this provide a plane for the power-stage currents to flow, but it also represents a thermally conductive path

away from the heat-generating device.

9.4.2 Layout Example

Cin1

Cin2

Cout1

Cout2

Rfbb

Rfbt

Cvcc

Rrt

Rboot

U1

Figure 9-12. Typical Layout

www.ti.com

TLVM13610

SLVSH63 – FEBRUARY 2023

Copyright © 2023 Texas Instruments Incorporated

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