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ADC34RF52 bảng dữ liệu(PDF) 73 Page - Texas Instruments

tên linh kiện ADC34RF52
Giải thích chi tiết về linh kiện  ADC34RF52 Quad Channel 14-bit 1.5-GSPS RF Sampling Data Converter
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Trang chủ  http://www.ti.com
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ADC34RF52 bảng dữ liệu(HTML) 73 Page - Texas Instruments

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Figure 7-73. Register 0x5D (JESD page)
7
6
5
4
3
2
1
0
K in ILA
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 7-76. Register 0x5D Field Descriptions
Bit
Field
Type
Reset
Description
7-0
K in ILA
R/W
0
These bits set K in the ILA sequence. Register value is actual K
value -1 (0x0F = K(15))
Figure 7-74. Register 0x7A (JESD page)
7
6
5
4
3
2
1
0
JESD LANE POL INV
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 7-77. Register 0x7A Field Descriptions
Bit
Field
Type
Reset
Description
7-0
JESD LANE POL INV
R/W
00000000
This register inverts the polarity of the individual SERDES output
lanes. Register bit D0 corresponds to SERDES lane DOUT0, D1
to DOUT1 etc
0: Output polarity as is
1: Output polarity inverted
Figure 7-75. Register 0x80/81/82/83 (JESD page)
ADDR
7
6
5
4
3
2
1
0
0x80
0
LANE DOUT1 SEL
0
LANE DOUT0 SEL
0x81
0
LANE DOUT3 SEL
0
LANE DOUT2 SEL
0x82
0
LANE DOUT5 SEL
0
LANE DOUT4 SEL
0x83
0
LANE DOUT7 SEL
0
LANE DOUT6 SEL
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 7-78. Register 0x80/81/82/83 Field Descriptions
Bit
Field
Type
Reset
Description
7,3
0
R/W
0
Must write 0
6-4
LANE DOUT1/3/5/7 SEL
R/W
000
These register bits control the output mux. Any physical serdes
output lane (DOUTx) can be connected to any JESD digital
stream. By default lane DOUT0 is connected to JESD stream 0,
lane DOUT1 to JESD stream 1 etc.
0: JESD stream 0
1: JESD stream 1
...
7: JESD stream 7
2-0
LANE DOUT0/2/4/6 SEL
R/W
000
Figure 7-76. Register 0x84 (JESD page)
7
6
5
4
3
2
1
0
0
0
0
0
0
0
JESD PLL FACTOR
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 7-79. Register 0x84 Field Descriptions
Bit
Field
Type
Reset
Description
7-2
0
R/W
0
Must write 0
1-0
JESD PLL FACTOR
R/W
00
This register bit must be set for 12-bit output LMFS = 8-4-8-10
only.
0: all other JESD LMFS modes
1: Set for LMFS = 8-4-8-10
www.ti.com
ADC34RF52
SBASAI7 – MARCH 2023
Copyright © 2023 Texas Instruments Incorporated
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Product Folder Links: ADC34RF52



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