MB90F474LPF datasheet(65/118 Pages) FUJITSU

65 / 118 page

MB90470 Series

14. Watchdog Timer

The watchdog timer is a 2-bit counter that uses a count clock signal output by the timer base timer or watch

timer and will reset the CPU unless cleared within a specified period of time.

(1) Register List

(2) Block Diagram

Watchdog timer control register (WDTC)

0000A8H

Default value

(

 )

( X )

( R )

( X )

( R )

( X )

( R )

( X )

( W )

( 1 )

( W )

( 1 )

( W )

( 1 )

Reserved

( R )

( X )

PONR

WRST

ERST

SRST

WTE

WT1

WT0

PONR STBR WRST ERST SRST WTE

WT1

WT0

× 21 × 22

× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218

× 21

SCLK

HCLK signal / 2

CLR

× 22

× 28 × 29 × 210 × 211 × 212 × 213 × 214 × 215 × 216 × 217 × 218

Watchdog timer control register (WDTC)

Watch timer control register

(WT0) WDCS bit

Clock select register

(CKSCR) SCM bit

Watch mode start

Time base timer

mode start

Sleep mode start

Hold status start

Watchdog timer

CLR and start

Counter clear

control circuit

Watchdog reset

generator circuit

Internal reset

generator

circuit

2-bit counter

Count

clock

selector

Stop mode start

Clear

Time base counter

HCLK : Oscillator clock

SCLK : Sub-clock

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