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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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ISO721 bảng dữ liệu(PDF) 4 Page - Texas Instruments |
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ISO721 bảng dữ liệu(HTML) 4 Page - Texas Instruments |
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4 / 22 page  www.ti.com ELECTRICAL CHARACTERISTICS: V CC1 and VCC2 5-V OPERATION SWITCHING CHARACTERISTICS: V CC1 and VCC2 5-V OPERATION ISO721, ISO721M ISO722, ISO722M SLLS629B – JANUARY 2006 – REVISED MAY 2006 over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Quiescent 0.5 1 ICC1 VCC1 supply current VI = VCC or 0 V, No load mA 25 Mbps 2 4 ISO722/722M EN at VCC 200 µA Sleep Mode VI = VCC or 0 V, No load ICC2 VCC2 supply current EN at 0 V or Quiescent 8 12 ISO721/721M mA 25 Mbps VI = VCC or 0 V, No load 10 14 IOH = -4 mA, See Figure 1 VCC – 0.8 4.6 VOH High-level output voltage V IOH = –20 µA, See Figure 1 VCC – 0.1 5 IOL = 4 mA, See Figure 1 0.2 0.4 VOL Low-level output voltage V IOL = 20 µA, See Figure 1 0 0.1 VI(HYS) Input voltage hysteresis 150 mV IIH High-level input current EN, IN at 2 V 10 µA IIL Low-level input current EN, IN at 0.8 V –10 High-impedance output IOZ ISO722, ISO722M EN, IN at VCC 1 µA current CI Input capacitance to ground IN at VCC, VI = 0.4 sin (4E6πt) 1 pF CMTI Common-mode transient immunity VI = VCC or 0 V, See Figure 5 25 50 kV/ µs over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tPLH Propagation delay, low-to-high-level output 13 17 24 tPHL Propagation delay , high-to-low-level output ISO72x 13 17 24 ns tsk(p) Pulse skew |tPHL– tPLH| 0.5 2 EN at 0 V, See Figure 1 tPLH Propagation delay, low-to-high-level output 8 10 16 tPHL Propagation delay, high-to-low-level output ISO72xM 8 10 16 tsk(p) Pulse skew |tPHL– tPLH| 0.5 1 tsk(pp)(1) Part-to-part skew 0 3 ns tr Output signal rise time 1 EN at 0 V, ns See Figure 1 tf Output signal fall time 1 Sleep-mode propagation delay, tpHZ 6 8 15 ns high-level-to-high-mpedance output See Figure 2 Sleep-mode propagation delay, tpZH 3.5 4 8 µs high-impedance-to-high-level output ISO722 ISO722M Sleep-mode propagation delay, tpLZ 5.5 8 15 ns low-level-to-high-impedance output See Figure 3 Sleep-mode propagation delay, tpZL 4 5 8 µs high-impedance-to-low-level output tfs Failsafe output delay time from input power loss See Figure 4 3 µs 100 Mbps NRZ data input, See Figure 6 2 ISO72x 100 Mbps unrestricted bit run length data 3 input, See Figure 6 tjit(PP) Peak-to-peak eye-pattern jitter ns 150 Mbps NRZ data input, See Figure 6 1 ISO72xM 150 Mbps unrestricted bit run length data 2 input, See Figure 6 (1) tsk(PP) is the magnitude of the difference in propagation delay times between any specified terminals of two devices when both devices operate with the same supply voltages, at the same temperature, and have identical packages and test circuits. 4 Submit Documentation Feedback |
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