STE2004DIE2 datasheet(37/66 Pages) STMICROELECTRONICS

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STE2004

INSTRUCTION SET

Two different instructions formats are provided:

- With D/C set to LOW : commands are sent to the Control circuitry.

- With D/C set to HIGH : the Data RAM is addressed.

Two different instruction set are embedded: the STE2001-like instruction set and the extended instruction

set. To select the STE2001-like instruction set the EXT pad has to be connected to a logic LOW (connect

to GND). To select the he extended instruction the EXT pad has to be connected to a logic HIGH (connect

to VDD1).

The instructions have the syntax summarized in Table 1 (basic-set) and Table 2 (extended set)

5.1 Reset (RES)

At power-on, all internal registers are configured with the default value. The RAM content is not defined.

A Reset pulse on RES pad (active low) re-initialize the internal registers content (see Tables 3,4,5,&6).

Every on-going communication with the host controller is interrupted, applying a reset pulse. After the

power-on, the Software Reset instruction can be used to re-load the reset configuration into the internal

registers.

The Default configurations is:

A MEMORY BLANK instruction can be executed to clear the DDRAM content.

5.2 Power Down (PD = 1)

When at Power Down, all LCD outputs are kept at VSS (display off). Bias generator and VLCD generator

are OFF (VLCDOUT output is discharged to VSS, and then is possible to disconnect VLCDOUT). The internal

Oscillator is in off state. An external clock can be provided. The RAM contents is not cleared.

5.3 Memory Blanking Procedure

This instruction allows to fill the memory with "blank" patterns, in order to delete patterns randomly gener-

ated in memory when starting up the device. This instruction substitutes (102X8) single "write" instruc-

tions. It is possible to program "Memory Blanking Procedure" only under the following conditions:

- PD bit

= 0

No instruction can be programmed for a period equivalent to 102X8 internal write cycles (102X8X1/fclock).

The start of Memory blanking procedure will be between one and two fclock cycles from the last active

edge (E fallig edge for the parallel interface, last SCLK rising edge for the Serial & SPI interfaces, last SCL

rising edge for the I2C interface).

5.4 Checker Board Procedure

This instruction allows to fill the memory with "checker-board" pattern. It is mainly intended to developers,

who can now simply obtain complex module test configuration by means of a single instruction. It is pos-

sible to program "Checker Board Procedure" only under the following conditions:

- PD bit

= 0

- Horizontal addressing (V = 0)

- Normal instruction set (H[1:0] = 0)

- Normal display (MX = MY = 0)

- Display blank (E = D = 0)

- Address counter X[6: 0] = 0 and Y[4: 0] = 0

- Temperature coefficient (TC[1: 0] = 0)

- Bias system (BS[2: 0] = 0)

- Multiplexing Ratio (M[1:0]=0 - MUX 65)

- Frame Rate (FR[1:0]=”75Hz”)

- Power Down (PD = 1)

- Dual Partial Display Disabled (PE=0)

- VOP=0

- Y-CARRIAGE=8

- X-CARRIAGE=101

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