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AM85C30 bảng dữ liệu(PDF) 48 Page - Advanced Micro Devices |
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AM85C30 bảng dữ liệu(HTML) 48 Page - Advanced Micro Devices |
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48 / 68 page ![]() AMD 48 Am85C30 1 TdRXC(REQ) RXC ↑ W/REQ Valid Delay 8 12 TcPc (Note 2) 2 TdRXC(W) RXC ↑ to Wait Inactive Delay 8 14 TcPc (Notes 1, 2) 3 TdRXC(SY) RxC ↑ to SYNC Valid Delay 4 7 TcPc (Note 2) 4 TdRXC(INT) RxC ↑ to INT Valid Delay 10 16 TcPc (Notes 1, 2) 5 TdTXC(REQ) TxC ↓ to W/REQ Valid Delay 5 8 TcPc (Note 3) 6 TdTXC(W) TxC ↓ to Wait Inactive Delay 5 11 TcPc (Notes 1, 3) 7a TdTXC(DRQ) TxC ↓ to DTR/REQ Valid Delay 4 7 TcPc (Note 3) 7b TdTXC(EDRQ) TxC ↓ to DTR/REQ Valid Delay 5 8 TcPc (Notes 3, 4) 8 TdTXC(INT) TxC ↓ to INT Valid Delay 6 10 TcPc (Notes 1, 3) 9 TdSY(INT) SYNC Transition to INT Valid 2 6 TcPc Delay (Note 1) 10 TdEXT(INT) DCD or CTS Transition to INT 2 6 TcPc Valid Delay (Note 1) 1 TdRXC(REQ) RXC ↑ W/REQ Valid Delay 8 12 8 12 TcPc (Note 2) 2 TdRXC(W) RXC ↑ to Wait Inactive Delay 8 14 8 14 TcPc (Notes 1, 2) 3 TdRXC(SY) RxC ↑ to SYNC Valid Delay 4 7 4 7 TcPc (Note 2) 4 TdRXC(INT) RxC ↑ to INT Valid Delay 10 16 10 16 TcPc (Notes 1, 2) 5 TdTXC(REQ) TxC ↓ to W/REQ Valid Delay 5 8 5 8 TcPc (Note 3) 6 TdTXC(W) TxC ↓ to Wait Inactive Delay 5 11 5 11 TcPc (Notes 1, 3) 7a TdTXC(DRQ) TxC ↓ to DTR/REQ Valid Delay 4 7 4 7 TcPc (Note 3) 7b TdTXC(EDRQ) TxC ↓ to DTR/REQ Valid Delay 5 8 5 8 TcPc (Notes 3, 4) 8 TdTXC(INT) TxC ↓ to INT Valid Delay 6 10 6 10 TcPc (Notes 1, 3) 9 TdSY(INT) SYNC Transition to INT Valid 2 6 2 6 TcPc Delay (Note 1) 10 TdEXT(INT) DCD or CTS Transition to INT 2 6 2 6 TcPc Valid Delay (Note 1) Notes: 1. Open-drain output, measured with open-drain test load. 2. RxC is RTxC or TRxC, whichever is supplying the receive clock. 3. TxC is TRxC or RTxC, whichever is supplying the transmit clock. 4. Parameter applies to Enhanced Request mode only. No. Parameter Symbol Parameter Description 8.192 MHz 10 MHz Min Max Min Max Unit No. Parameter Symbol Parameter Description 16.384 MHz Min Max Unit SWITCHING CHARACTERISTICS over MILITARY/INDUSTRIAL operating range (continued) System Timing (see Figure 20) |
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