DP83955AV datasheet(13/54 Pages) NSC

13 / 54 page

30 Pin Description (Continued)

Driver

Description

Name

Type

INTER-LERIC BUS PINS

(Continued)

IRE

B Z

nter-LERIC Enable When asserted as an output this signal provides an activity framing enable for the

serial data stream The signal is asserted by a LERIC when it is receiving data from one of its network

segments The default condition of this signal is to be an input In this state it may be driven by other

devices on the Inter-LERIC bus

IRC

B Z

nter-LERIC Clock When asserted as an output this signal provides a clock signal for the serial data

stream Data (IRD) is changed on the falling edge of the clock The signal is asserted by a LERIC when it

is receiving data from one of its network segments The default condition of this signal is to be an input

When an input IRD is sampled on the rising edge of the clock In this state it may be driven by other

devices on the Inter-LERIC bus

COLN

B Z

COL

lision on Port N This denotes that a collision is occurring on the port receiving the data packet (Port

N) The default condition of this signal is to be an input In this state it may be driven by other devices on

the Inter-LERIC bus

CLK

20 MHz Clock Input This input is used to generate the LERIC’s timing reference for the state machines

and phase lock loop decoder The 20 MHz clock should have a 001% frequency tolerance and 40% –

60% duty cycle or better (ie 5050 duty cycle)

POWER AND GROUND PINS

VCC

Positive Supply

GND

Negative Supply

EXTERNAL DECODER PINS

RXM

Receive Data Manchester Format

This output makes the data in Manchester format received by port

N available for test purposes If not used for testing this pin should be left open

Note

TT e TT

L compatible

B e B

i-directional

C e C

MOS compatible

OD e O

pen Drain

I e I

nput

O e O

utput

Z e

TRI-STATE

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