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M95128-DF bảng dữ liệu(PDF) 37 Page - STMicroelectronics

tên linh kiện M95128-DF
Giải thích chi tiết về linh kiện  128-Kbit serial SPI bus EEPROM with high-speed clock
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M95128-DF bảng dữ liệu(HTML) 37 Page - STMicroelectronics

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10.3
UFDFPN8 (DFN8) package information
UFDFPN8 is an 8-lead, 2 × 3 mm, 0.55 mm thickness ultra thin profile fine pitch dual flat package.
Figure 27. UFDFPN8 - Outline
Top view
Pin #1
ID marking
Side view
Seating plane
eee
ccc
C
C
C
C
C
B
A
1 2
N
D
E
aaa
aaa
A
A1
A3
2x
2x
Datum A
Terminal tip
Detail “A”
Even terminal
L1
L3
L
e
e/2
Pin #1
ID marking
Bottom view
See Detail “A”
e
e
1 2
ND-1 x
D2
L1
L3
E2
K
L
b
1.
Maximum package warpage is 0.05 mm.
2.
Exposed copper is not systematic and can appear partially or totally according to the cross section.
3.
Drawing is not to scale.
4.
The central pad (the area E2 by D2 in the above illustration) must be either connected to VSS or left floating
(not connected) in the end application.
M95128-W M95128-R M95128-DF
UFDFPN8 (DFN8) package information
DS1356 - Rev 20
page 37/48



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