UPSD3422_V01 datasheet(170/300 Pages) STMICROELECTRONICS

170 / 300 page

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USB interface

UPSD3422, UPSD3433, UPSD3434, UPSD3454

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USB control register (UCTL)

The USB control register (see Table 120) is used to enable the SIE, make the Endpoint

FIFOs visible in the XDATA space and for generating a remote wakeup signal. Upon a

reset, the USB module is disabled and must be enabled by the CPU for communication

with the host over the USB.

Table 120.

USB control register (UCTL 0ECh, reset value 00h)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

–

USBEN

VISIBLE

WAKEUP

Table 121.

UCTL register bit definition

Bit

Symbol

R/W

Definition

–

Reserved

–

Reserved

–

Reserved

–

Reserved

–

Reserved

USBEN

R/W

USB Enable

When this bit is set, the USB function is enabled and the SIE

responds to tokens from the host. When this bit is clear, the

USB function is disabled and does not respond to any tokens

from the host.

Note: A USB reset does not clear this bit. Disabling and

enabling the SIE using this bit resets part of the USB SIE state

machine and some of the bits in the USTA and UCON

registers.

1VISIBLE

R/W

USB FIFO VISIBLE

When this bit is set, the selected USB FIFO is accessible

(visible) in the XDATA space.

WAKEUP

R/W

Remote Wakeup Enable

This bit forces a resume or “K” state on the USB data lines to

initiate a remote wake-up. The CPU is responsible for

controlling the timing of the forced resume that must be

between 10ms and 15ms. Setting this bit will not cause the

RESUMF Bit to be set.

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