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UPSD3422 bảng dữ liệu(PDF) 120 Page - STMicroelectronics |
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UPSD3422 bảng dữ liệu(HTML) 120 Page - STMicroelectronics |
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120 / 300 page ![]() Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s) IrDA interface UPSD3422, UPSD3433, UPSD3434, UPSD3454 120/300 The UART1 serial channel can operate in one of four different modes as shown in Table 64 on page 108 in Section 21: Serial UART interfaces on page 107. However, when UART1 is used for IrDA communication, UART1 must operate in Mode 1 only, to be compatible with IrDA protocol up to 115.2k bps. The IrDA interface will support baud rates generated from Timer 1 or Timer 2, just like standard UART serial communication, but with one restriction. The transmit baud rate and receive baud rate must be the same (cannot be different rates as is allowed by standard UART communications). The IrDA Interface is disabled after a reset and is enabled by setting the IRDAEN Bit in the SFR named IRDACON (Table 70 on page 120). When IrDA is disabled, the UART1's RxD and TxD signals will bypass the internal IrDA logic and instead they are routed directly to the pins RxD1 and TxD1 respectively. When IrDA is enabled, the IrDA pulse shaping logic is active and resides between UART1 and the pins RxD1 and TxD1 as shown in Figure 38 on page 119. 22.1 Baud rate selection The IrDA standard only supports 2.4, 9.6, 19.2, and 115.2kbps. Table 73 on page 121 informs the IrDA Interface of the baud rate of UART#1 so that it can perform pulse modulation properly. It may not be necessary to implement the BR[3:0] bits in the IRDACON register if the IrDA Interface obtains the proper timing from UART#1. Table 70. IRDACON register bit definition (SFR CEh, reset value 0Fh) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 – IRDAEN PULSE CDIV4 CDIV3 CDIV2 CDIV1 CDIV0 Table 71. IRDACON register bit definition Bit Symbol R/W Definition 7 – – Reserved 6 IRDAEN RW IrDA Enable 0 = IrDA Interface is disabled 1 = IrDA is enabled, UART1 outputs are disconnected from Port 1 (or Port 4) 5PULSE RW IrDA Pulse Modulation Select 0 = 1.627µs 1 = 3/16 bit time pulses 4-0 CDIV[4:0] RW Specify Clock Divider (see Table 74 on page 122) Table 72. Baud rate selection register (SFR xxh, reset value xxh) Bit Symbol R/W Definition 7:4 BR[3:0] R,W Specify Baud Rate (see Table 73) 3:2 PULSE R,W IrDA Pulse Modulation Select 0 = 3/16 bit time pulses (not recommended) 1 = 1.627µs 1:0 IRDAEN R,W 0 = IrDA Interface is disabled 1 = IrDA is enabled, UART#1 outputs are disconnected from Port 1 (or Port 4) Obsolete Product(s) - Obsolete Product(s) |
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