SN65LVDS86AQ, SN75LVDS86A

FlatLink RECEIVER

SLLS318C − NOVEMBER 1998 − REVISED JULY 2006

5

POST OFFICE BOX 655303

electrical characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

VIT+

Positive-going differential input threshold voltage

100

mV

VIT−

Negative-going differential input threshold voltage‡

−100

mV

VOH

High-level output voltage

IOH = − 4 mA

2.4

V

VOL

Low-level output voltage

IOL = 4 mA

0.4

V

Disabled,

All inputs to GND

280

µA

Enabled,

AnM = 1.4 V,

AnP = 1 V,

tc = 15.38 ns

33

40

ICC

Quiescent current (average)

Enabled,

CL = 8 pF,

Grayscale pattern (see Figure 3),

tc = 15.38 ns

43

mA

Enabled,

CL = 8 pF,

Worst-case pattern (see Figure 4)

tc = 15.38 ns

68

IIH

High-level input current (SHTDN)

VIH = VCC

±20

µA

IIL

Low-level input current (SHTDN)

VIL = 0

SN75LVDS86A

±20

A

IIL

Low-level input current (SHTDN)VIL = 0

SN65LVDS86AQ

±25

µA

II

Input current A inputs

0

≤ VI ≤ 2.4 V

±20

µA

IOZ

High-impedance output current

VO = 0 or VCC

±10

µA

† All typical values are at VCC = 3.3 V, TA = 25°C.

‡ The algebraic convention, in which the less-positive (more-negative) limit is designated minimum, is used in this data sheet for the negative-going

input voltage threshold only.

switching characteristics over recommended operating conditions (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP†

MAX

UNIT

tsu

Setup time, D0–D20 to CLKOUT

↓

CL = 8 pF, See Figure 5

5

ns

th

Data hold time, CLKOUT

↓ to D0–D20

CL = 8 pF, See Figure 5

5

ns

t(RSKM) Receiver input skew margin§ (see Figure 7)

tc = 15.38 ns (± 0.2%),

|Input clock jitter| < 50 ps¶,

550

700

ps

td

Delay time, CLKIN

↑ to CLKOUT↓ (see Figure 7)

VCC = 3.3 V,

tc = 15.38 ns (± 0.2%), TA = 25°C

3

5

7

ns

ten

Enable time, SHTDN to phase lock

See Figure 7

1

ms

tdis

Disable time, SHTDN to off state

See Figure 8

400

ns

tt

Transition time, output (10% to 90% tr or tf) (data only)

CL = 8 pF

3

ns

tt

Transition time, output (10% to 90% tr or tf) (clock only)

CL = 8 pF

1.5

ns

tw

Pulse duration, output clock

0.50 tc

ns

† All typical values are at VCC = 3.3 V, TA = 25°C.

§ The parameter t(RSKM) is the timing margin available to allocate to the transmitter and interconnection skews and clock jitter. The value of this

parameter at clock periods other than 15.38 ns can be calculated from tRSKM = tc/14 – 550 ps.

¶ |Input clock jitter| is the magnitude of the change in input clock period.