KSZ9567RTXI datasheet(54/232 Pages) MICROCHIP

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KSZ9567R

DS00002329D-page 54

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4.8

Clocking

4.8.1

PRIMARY CLOCK

The device requires a 25MHz reference clock input at the XI pin. This clock is internally multiplied up and used to clock

all of the internal logic and switching functions. It is also normally used as to clock the PHY transmit paths. This clock

may be supplied by connecting a crystal between the XI and XO pins (and appropriate load capacitors to ground). Alter-

natively, an external CMOS clock signal may drive XI, while XO is left unconnected. The XI/XO block is powered from

AVDDH.

4.8.2

MAC INTERFACE CLOCKS

The MII interface is clocked asymmetrically, with the PHY device driving both the RX_CLKx receive clock and the TX_-

CLKx transmit clock to the MAC device. Each MII port may be configured at reset by a strapping option to take the role

of either the PHY or the MAC. RX_CLKx and TX_CLKx are therefore either both inputs or both outputs, depending on

the MII mode.

The RMII interface uses a single 50MHz clock. This REFCLK may be sourced either from the KSZ9567R or from the

connected device. A strapping option is used to select the mode for each port. “Normal Mode” is the mode where the

other device supplies the clock, and the clock is an input to the REFCLKIx pin of the device. “Clock Mode” is the mode

where the KSZ9567R generates the 50MHz clock on the REFCLKOx pin.

The RGMII interface employs source synchronous clocking, so it is symmetrical and does not require a mode selection.

An output clock is generated on the RX_CLKx pin, while an input clock is received on the TX_CLKx pin. The clock

speed scales with the interface data rate - either 10, 100 or 1000 Mbps. A strapping option is used to select between

the 100 and 1000 Mbps speeds. If the 10 Mbps rate is required, then a register setting is used to set that speed.

The MAC interfaces are powered from VDDIO.

4.8.3

SERIAL MANAGEMENT INTERFACE CLOCK

Whether configured to be SPI, I2C or MIIM, the KSZ9567R is always a slave and receives the clock as an input. The

serial management interface is powered from VDDIO.

4.8.4

SYNCHRONOUS ETHERNET AND SYNCLKO

An output clock is provided on the SYNCLKO pin. By default it is derived from the 25MHz input reference clock on XI,

but the source can be selected to be the recovered clock from any of the PHY ports. This recovered clock may then feed

an external device with a low bandwidth PLL and hold-over feature for use in Synchronous Ethernet applications. A

25MHz clock derived from SYNCLKO may then be used as the input to XI.

The output frequency choices are 25MHz (default) and 125MHz. If not needed, this output clock can also be disabled.

SYNCLKO is controlled via the Output Clock Control Register, and is powered from VDDIO.

Note:

Refer to Section 3.2.1, "Configuration Straps," on page 16 for additional information on using configuration

straps.

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