KSZ9567RTXI datasheet(18/232 Pages) MICROCHIP

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KSZ9567R

DS00002329D-page 18

 2017-2019 Microchip Technology Inc.

4.0

FUNCTIONAL DESCRIPTION

This section provides functional descriptions for the following:

• Physical Layer Transceiver (PHY)

• LEDs

• Media Access Controller (MAC)

• Switch

• IEEE 1588 Precision Time Protocol

• Audio Video Bridging and Time Sensitive Networks

• NAND Tree Support

• Clocking

• Power

• Power Management

• Management Interface

• In-Band Management

• MAC Interface (RGMII/MII/RMII Port 6-7)

4.1

Physical Layer Transceiver (PHY)

Ports 1 through 5 include completely integrated triple-speed (10BASE-Te, 100BASE-TX, 1000BASE-T) Ethernet phys-

ical layer transceivers for transmission and reception of data over standard four-pair unshielded twisted pair (UTP), CAT-

5 or better Ethernet cable.

The device reduces board cost and simplifies board layout by using on-chip termination resistors for the four differential

pairs, eliminating the need for external termination resistors. The internal chip termination and biasing provides signifi-

cant power savings when compared with using external biasing and termination resistors.

The device can automatically detect and correct for differential pair misplacements and polarity reversals, and correct

for propagation delay differences between the four differential pairs, as specified in the IEEE 802.3 standard for

1000BASE-T operation.

4.1.1

1000BASE-T TRANSCEIVER

The 1000BASE-T transceiver is based on a mixed-signal/digital signal processing (DSP) architecture, which includes

the analog front-end, digital channel equalizers, trellis encoders/decoders, echo cancelers, cross-talk cancelers, a pre-

cision clock recovery scheme, and power-efficient line drivers.

4.1.1.1

Analog Echo Cancellation Circuit

In 1000BASE-T mode, the analog echo cancellation circuit helps to reduce the near-end echo. This analog hybrid circuit

relieves the burden of the ADC and the adaptive equalizer. This circuit is disabled in 10BASE-Te/100BASE-TX mode.

4.1.1.2

Automatic Gain Control (AGC)

In 1000BASE-T mode, the automatic gain control circuit provides initial gain adjustment to boost up the signal level. This

pre-conditioning circuit is used to improve the signal-to-noise ratio of the receive signal.

4.1.1.3

Analog-to-Digital Converter (ADC)

In 1000BASE-T mode, the analog-to-digital converter digitizes the incoming signal. ADC performance is essential to the

overall performance of the transceiver. This circuit is disabled in 10BASE-Te/100BASE-TX mode.

4.1.1.4

Timing Recovery Circuit

In 1000BASE-T mode, the mixed signal clock recovery circuit, together with the digital phase locked loop (PLL), is used

to recover and track the incoming timing information from the received data. The digital PLL has very low long-term jitter

to maximize the signal-to-noise ratio of the receive signal.

The 1000BASE-T slave PHY must transmit the exact receive clock frequency recovered from the received data back to

the 1000BASE-T master PHY. Otherwise, the master and slave will not be synchronized after long transmission. This

also helps to facilitate echo cancellation and NEXT removal.

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