47L64 datasheet(16/29 Pages) MICROCHIP

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2019-2020 Microchip Technology Inc.

Preliminary

DS20006168B-page 16

47L64

4.3.2

READ OPERATION

When the SRAM array is selected and the R/W bit is

set to ‘1’, a read operation is selected. For read

operations, the array address is not transmitted,

instead, the internal Address Pointer is used to

determine where the read starts.

During read operations, the master device generates

the Acknowledge bit after each data byte, and it is this

bit which determines whether the operation will

continue or end. A ‘0’ (Acknowledge) bit requests

more data and continues the read, while a ‘1’ (No

Acknowledge) bit ends the read operation.

4.3.2.1

Current Address Read

The current address read operation relies on the

current value of the Address Pointer to determine from

where to start reading. The Address Pointer is

automatically incremented after each data byte is read

or written. Therefore, if the previous access was to

address n (where n is any legal address), the next

current address read operation would access data

beginning with address n+1.

Upon receipt of the control byte with the R/W bit set to

‘1’, the 47L64 issues an Acknowledge and transmits

the 8-bit data byte. The master will not acknowledge

the transfer, but does generate a Stop condition and

the 47L64 discontinues transmission (Figure 4-6).

FIGURE 4-6:

SRAM CURRENT

ADDRESS READ

4.3.2.2

Random Read

Random read operations allow the master to access

any memory location in a random manner. To perform

this type of read operation, first the Address Pointer

must be set. This is done by sending the array address

to the 47L64 as part of a write operation (R/W bit set

to ‘0’). After the array address is sent, the master

generates

Start

condition

following

the

Acknowledge. This terminates the write operation, but

not before the Address Pointer has been set. Then,

the master issues the SRAM control byte again but

with the R/W bit set to a ‘1’. The 47L64 will then issue

an Acknowledge and transmit the 8-bit data byte. The

master will not Acknowledge the transfer but does

generate a Stop condition, which causes the 47L64 to

discontinue transmission (Figure 4-7). After a random

read operation, the Address Pointer will point to the

address location following the one that was just read.

4.3.2.3

Sequential Read

Sequential reads are initiated in the same way as a

random read except that after the 47L64 transmits the

first data byte, the master issues an Acknowledge as

opposed to the Stop condition used in a random read.

The Acknowledge directs the 47L64 to transmit the

next sequentially addressed 8-bit byte (Figure 4-8).

Following the final byte transmitted to the master, the

master will NOT generate an Acknowledge but will

generate a Stop condition. To provide sequential

reads, the 47L64 increments the internal Address

Pointer by one after the transfer of each data byte.

This allows the entire memory contents to be serially

read during one operation. The Address Pointer will

automatically roll over at the end of the array to

address 0x0000 after the last data byte in the array

has been transferred.

FIGURE 4-7:

SRAM RANDOM READ

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

DATA

1 1

0 0 A A 1

BYTE

2 1 1

BUS ACTIVITY

MASTER

SDA LINE

BUS ACTIVITY

CONTROL

BYTE

ADDRESS

HIGH BYTE

ADDRESS

LOW BYTE

CONTROL

BYTE

DATA

BYTE

S 1 0 1 0 A A 0

2 1

S 1 0 1 0 A A 1

2 1

X X X

X = Don’t Care

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