47L64 datasheet(14/29 Pages) MICROCHIP

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Preliminary

DS20006168B-page 14

47L64

4.3

SRAM ARRAY

The SRAM array is the only user-accessible memory

panel available on the 47L64. The EEPROM array,

which can only be directly accessed through test mode

operations, provides nonvolatile storage to back up

the SRAM data.

To select the SRAM array, the master device must use

the respective 4-bit op code, ‘1010’, when transmitting

the control byte.

4.3.1

WRITE OPERATION

When the SRAM array is selected and the R/W bit in

the control byte is set to ‘0’, a write operation is

selected and the next two bytes received are

interpreted as the array address. The Most Significant

address bits are transferred first, followed by the Least

Significant bits, and are shifted directly into the internal

Address Pointer. The Address Pointer determines

where in the SRAM array the next read or write

operation begins.

Data is stored into the SRAM array as soon as it is

received, specifically on the rising edge of SCL during

each Acknowledge bit. If a write operation is aborted

for any reason, all received data will already be stored

in SRAM, except for the last data byte if the rising

edge of SCL during the Acknowledge for that byte has

not yet been reached.

4.3.1.1

Byte Write

After the 47L64 has received the 2-byte array address,

responding with an Acknowledge after each address

byte, the master device will transmit the data byte to

be written into the addressed memory location. The

47L64 acknowledges again and the master generates

a Stop condition (Figure 4-4). The data byte is latched

into the SRAM array on the rising edge of SCL during

the Acknowledge.

After a byte write command, the internal Address

Pointer will point to the address location following the

location that was just written.

4.3.1.2

Sequential Write

To write multiple data bytes in a single operation, the

SRAM write control byte, array address, and the first

data byte are transmitted to the 47L64 in the same

way as for a byte write. However, instead of

generating a Stop condition, the master transmits

additional data bytes (Figure 4-5). Upon receipt of

each byte, the 47L64 responds with an Acknowledge,

during which the data is latched into the SRAM array

on the rising edge of SCL, and the Address Pointer is

incremented by one. Sequential write operations are

limited to the address 0x1FFF, and if the master

should transmit enough bytes further, the Address

Pointer will roll over to 0x0000 and continue writing.

There is no limit to the number of bytes that can be

written in a single command.

In the event that the WP pin is set high, writes to

addresses in the upper 1/4 portion of the array will not

be allowed. Attempts to write in that region will receive

an ACK response from the device for the address

bytes, but will receive a NACK for data bytes written

(see Table 4-1).

Note: If an AutoStore is triggered during an

SRAM read or write operation, the

operation is aborted in order to execute

the Store.

Note: If an attempt is made to write to a pro-

tected portion of the array, the device

will not respond with an Acknowledge

after the data byte is received, the cur-

rent operation will be terminated without

incrementing the Address Pointer, and

any data transmitted on the SDA line will

be ignored until a new operation is

begun with a Start condition.

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