STLC2500A datasheet(32/37 Pages) STMICROELECTRONICS

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Digital interfaces

STLC2500A

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Figure 13.

PCM interface timing

7.3

JTAG interface

The JTAG interface is compliant with the JTAG IEEE Standard 1149.1. It allows both the

boundary scan of the digital pins and the debug of the ARM7TDMI application when

connected with the standard ARM7 developments tools. It is also used for the industrial test

of the device.

Slot start (programmable for every

slot)

255

cycles

DData size

bit

Number of slots per frame

In master mode, the minimum frequency is 2 MHz

Table 21.

PCM interface timing

Symbol

Parameter

Min.

Typ.

Max.

Unit

tWCH

High period of PCM_CLK

200

tWCL

Low period of PCM_CLK

200

tWSH

High period of PCM_SYNC

200

tSSC

Setup time, PCM_SYNC high to

PCM_CLK low

100

tSDC

Setup time, PCM_A/B input valid to

PCM_CLK low

100

tHCD

Hold time, PCM_CLK low to

PCM_A/B input valid

100

tDCD

Delay time, PCM_CLK high to

PCM_A/B output valid

150

Table 20.

PCM interface parameters

Symbol

Parameter

Min.

Typ.

Max.

Unit

D02TL557

PCM_CLK

tWCL

PCM_SYNC

PCM_A/B in

PCM_B/A out

MSB

MSB-1

MSB-2

MSB-3

MSB-4

MSB

MSB-1

MSB-2

MSB-3

MSB-4

tSSC

tWCH

tWSH

tHCD

tSDC

tDCD

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