XRT83SL28IV datasheet(8/47 Pages) EXAR

8 / 47 page

XRT83SL28

8-CHANNEL E1 SHORT-HAUL LINE INTERFACE UNIT

REV. 1.0.0

RECEIVER SECTION

NAME

TYPE

DESCRIPTION

RLOS7

RLOS6

RLOS5

RLOS4

RLOS3

RLOS2

RLOS1

RLOS0

116

120

137

133

Receive Loss of Signal

When a receive loss of signal occurs, the RLOS pin will go "High" for a mini-

mum of one RCLK cycle. RLOS will remain "High" until the loss of signal con-

dition clears. See the Receive Loss of Signal section of this datasheet for

more details.

RCLK7

RCLK6

RCLK5

RCLK4

RCLK3

RCLK2

RCLK1

RCLK0

119

123

134

130

Receive Clock Output

RCLK is the recovered clock from the incoming data stream. If the incoming

signal is absent, RCLK maintains its timing by using an internal master clock

as its reference. RPOS/RNEG data can be updated on either edge of RCLK

selected by RCLKinv in the appropriate global register.

NOTE: RCLKinv is a global setting that applies to all 8 channels.

RPOS7

RPOS6

RPOS5

RPOS4

RPOS3

RPOS2

RPOS1

RPOS0

118

122

135

131

RPOS/RDATA Output

Receive digital output pin. In dual rail mode, this pin is the receive positive

data output. In single rail mode, this pin is the receive non-return to zero (NRZ)

data output.

RNEG/LCV7

RNEG/LCV6

RNEG/LCV5

RNEG/LCV4

RNEG/LCV3

RNEG/LCV2

RNEG/LCV1

RNEG/LCV0

117

121

136

132

RNEG/LCV Output

In dual rail mode, this pin is the receive negative data output. In single rail

mode, this pin is a Line Code Violation indicator. If a line code violation or a bi-

polar violation occur, the LCV pin will pull "High" for a minimum of one RCLK

cycle. LCV will remain "High" until there are no more violations.

XRT83SL28IV bảng dữ liệu(PDF) 8 Page - Exar Corporation

XRT83SL28IV bảng dữ liệu(HTML) 8 Page - Exar Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47

bảng dữ liệu tải về

Link URL