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AS1504 bảng dữ liệu(PDF) 4 Page - ams AG |
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AS1504 bảng dữ liệu(HTML) 4 Page - ams AG |
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4 / 17 page ![]() www.austriamicrosystems.com Revision 1.0 4 - 17 AS1504, AS1505 austriamicrosystems Data Sheet Switching Characteristics 5, 8 tCH Input Clock Pulse Width High Clock Level 15 ns tCL Low Clock Level 15 ns tDS Data Setup Time 5 ns tDH Data Hold Time 5 ns tCSS CSN Setup Time 10 ns tCSW CSN High Pulse Width 10 ns tRS Reset Pulse Width 60 ns tCSH CLK-Rise to CSN-Rise Hold Time 15 ns tCS1 CSN-Rise to Next Rising Clock Time 10 ns 1. Typ values are average readings at +25ºC. 2. VREFH can be any value between VDD and GND. 3. VREFL can be any value between VDD and GND. 4. With all DACs set to code 0x55h. Typical input resistance per DAC is 5kOhm with code 0x55h. 5. Guaranteed by design; not subject to production test. 6. VIN = 0V or VDD (CMOS); DAC outputs unloaded. PDISS is calculated as IDD x VDD. 7. Measured at an OUTx pin where an adjacent OUTx pin is making a full-scale voltage change. 8. See Figure 13 on page 9 for location of measured values. All input control voltages are specified with tR = tF = 2ns. Table 3. Electrical Characteristics (Continued) Symbol Parameter Conditions Min Typ 1 Max Unit |
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