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Revision 1.0

7 - 17

AS1504, AS1505

Data Sheet

Pin Assignments

7 Pinout

Pin Assignments

Figure 10. Pin Assignments (Top View)

Pin Descriptions

Table 4. Pin Descriptions

Pin Number

Pin Name

Description

(see Figure 10)

CLK

Serial Clock Input

. Positive-edge triggered.

CSN

Chip Select

. When this active-low pin goes high, the serial input register data is

decoded based on the address bits and loaded into the target DAC register.

GND

Ground

OUT1

DAC 1 Output

OUT2

DAC 2 Output

OUT3

DAC 3 Output

OUT4

DAC 4 Output

OUT5

DAC 5 Output

OUT6

DAC 6 Output

OUT7

DAC 7 Output

OUT8

DAC 8 Output

RSN

Reset

(AS1504 Only). Active-low asynchronous reset to mid-scale output setting.

SDI

Serial Data Input

SHDNN

Shutdown

. Active-low reference input open-circuit. All DAC outputs open-circuit.

Note:

DAC latch settings are maintained during shutdown.

Positive Supply Voltage

. +3 to +5V.

Common High-Side DAC Reference Input

Common Low-Side DAC Reference Input

(AS1505 Only).

1

AS1504

2

OUT1

3

OUT2

4

OUT3

5

OUT4

6

SHDNN

7

CSN

16

15

RSN

14

OUT8

13

OUT7

12

OUT6

11

OUT5

10

SDI

9

CLK

8

GND

1

AS1505

2

OUT1

3

OUT2

4

OUT3

5

OUT4

6

SHDNN

7

CSN

16

15

OUT8

14

OUT7

13

OUT6

12

OUT5

11

SDI

10

CLK

9

8

GND