MSP430 datasheet(6/88 Pages) TI

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6.5 Electrical Characteristics

all minimum and maximum values at TA = –40°C to +125°C and all typical values at TA = 25°C, PVDD = VDD = IOVDD =

1.8 V, external or internal VREFIO = 1.25 V, RLOAD = 50 kΩ to GND, CLOAD = 100 pF to GND, and digital inputs at IOVDD or

GND (unless otherwise noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

VOUT DAC STATIC PERFORMANCE

Resolution

AFE88101

Bits

AFE78101

INL

Integral nonlinearity(1)

AFE88101

–4

LSB

AFE78101

–2

DNL

Differential nonlinearity(1)

–1

LSB

TUE

Total unadjusted error(1)

TA = –40°C to +125°C

–0.07

0.07

%FSR

TA = –40°C to +85°C

–0.05

0.05

TA = 25°C

–0.04

0.04

ZCE

Zero code error

TA = –40°C to +125°C

–0.07

0.07

%FSR

TA = –40°C to +85°C

–0.05

0.05

TA = 25°C

–0.03

0.03

ZCE-TC Zero code error temperature coefficient

±3

ppm/°C

Offset error(1)

TA = –40°C to +125°C

–0.07

0.07

%FSR

TA = –40°C to +85°C

–0.05

0.05

TA = 25°C

–0.03

0.03

OE-TC

Offset error temperature coefficient (1)

±3

ppm/°C

Gain error(1)

TA = –40°C to +125°C

–0.04

0.04

%FSR

TA = –40°C to +85°C

–0.04

0.04

TA = 25°C

–0.03

0.03

GE-TC

Gain error temperature coefficient(1)

±3

ppm FSR/°C

FSE

Full-scale error

TA = –40°C to +125°C

–0.07

0.07

%FSR

TA = –40°C to +85°C

–0.06

0.06

TA = 25°C

–0.04

0.04

FSE-TC Full-scale error temperature coefficient

±3

ppm FSR/°C

VOUT DAC DYNAMIC PERFORMANCE

Output voltage settling time(4)

¼ to ¾ scale and ¾ to ¼ scale settling to ±2 LSB,

PVDD = VDD = 1.8 V, VREFIO = 1.25 V

µs

10-mV step settling to ±2 LSB,

PVDD = VDD = 1.8 V, VREFIO = 1.25 V

Slew rate(4)

Fullscale transition measured from 10% to 90%

V/µs

Output noise(4)

0.1 Hz to 10 Hz, DAC at midscale,

PVDD = VDD = 1.8 V, VREFIO = 1.25 V

0.25

LSBPP

100-kHz bandwidth, DAC at midscale,

PVDD = VDD = 1.8 V, VREFIO = 1.25 V

µVrms

Output noise density

Measured at 1 kHz, DAC at midscale,

PVDD = VDD = 1.8 V, VREFIO = 1.25 V

180

nV/√Hz

Measured at 1 kHz, DAC at midscale,

PVDD = 5 V, VREFIO = 1.25 V

260

Power supply rejection ratio (AC)

200-mV 50-Hz to 60-Hz sine wave superimposed on

power supply voltage, DAC at midscale.

Code change glitch impulse

Midcode ±1 LSB (including feedthrough)

PVDD = VDD = 1.8 V, VREFIO = 1.25 V

4.5

nV-s

Code change glitch magnitude

Midcode ±1 LSB (including feedthrough)

PVDD = 5 V, VREFIO = 1.25 V

1.5

Digital feedthrough

At SCLK = 1 MHz, DAC output at midscale

nV-s

AFE78101, AFE88101

SLASF21 – DECEMBER 2022

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