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ICS93701 bảng dữ liệu(PDF) 8 Page - Integrated Circuit Systems

tên linh kiện ICS93701
Giải thích chi tiết về linh kiện  DDR Phase Lock Loop Clock Driver
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ICS93701 bảng dữ liệu(HTML) 8 Page - Integrated Circuit Systems

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ICS93701
0417B—10/29/02
Recommended Layout for the ICS93701
General Layout Precautions:
Use copper flooded ground on the top signal layer under the
clock buffer The area under U1 on the right is an example.
Flood over the ground vias.
1)
Use power vias for power and ground. Vias 20 mil or
larger in diameter have lower high frequency impedance.
Vias for signals may be minimum drill size.
2)
Make all power and ground traces are as wide as the via
pad for lower inductance.
3)
VAA for pin 16 has a low pass RC filter to decouple the
digital and analog supplies. The 4.7uF capacitors may be
replaced with a single low ESR device with the same
total capacitance. VAA is routed on a outside signal
layer. Do not cut a power or ground plane and route in it.
4)
Notice that ground vias are never shared.
5)
When ever possible, VCC (net V2P5 in the schematic)
pins have a decoupling capacitor. Power is always routed
from the plane connection via to the capacitor pad to the
VCC pin on the clock buffer. Moats or plane cuts are not
used to isolate power.
6)
Differential mode clock output traces are routed:
a.
With a ground trace between the pairs. Trace is
grounded on both ends.
b.
Without a ground trace, clock pairs are routed with a
separation of at least 5 times the thickness of the
dielectric. If the dielectric thickness is 4.5 mil, the
trace separation is at least 18 mils.
Component Values:
Ref Desg.
Value
Description
Package
C1,C4,C5,
C7,C11,C12
.01uF
CERAMIC MLC
0603
C2,C3,C8,
C9
4.7uF
CERAMIC MLC
1206
C10
.22uF
CERAMIC MLC
0603
C6
2200pF
CERAMIC MLC
0603
R12
120
Ω
0603
R9
4.7
Ω
0603
U1
ICS93701AG
TSSOP48
C2
4.7uF
V2P5
FB_IN#
C3
4.7uF
V2A5
C9
4.7uF
C7
.01uF
V2P5
C16
.01uF
C10
.22uF
C1
.01uF
C5
.01uF
C11
.01uF
R12
120
1
2
V2A5
V2A5
CLK_IN#
U1
ICS93701
16
4
11
15
21
28
34
38
45
1
7
8
18
24
25
31
41
42
48
17
35
36
13
14
37
12
3
2
5
6
10
9
20
19
22
23
46
47
44
43
39
40
29
30
27
26
33
32
AVDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
AGND
FB_INT
FB_INC
CLK_INT
CLK_INC
SDA
SCL
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
FB_OUTT
FB_OUTC
C12
.01uF
C6
.0022pF
SCL
R9
4.7
1
2
C13
.01uF
SDA
C14
.01uF
FB_IN
C8
4.7uF
C15
.01uF
CLK_IN
C4
.01uF



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