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STM32W108CB bảng dữ liệu(PDF) 185 Page - STMicroelectronics |
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STM32W108CB bảng dữ liệu(HTML) 185 Page - STMicroelectronics |
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185 / 278 page ![]() STM32W108HB STM32W108CC STM32W108CB STM32W108CZ General-purpose timers Doc ID 16252 Rev 14 185/278 10.1.14 Timer synchronization The two timers can be linked together internally for timer synchronization or chaining. A timer configured in Master mode can reset, start, stop or clock the counter of the other timer configured in Slave mode. Figure 45 presents an overview of the trigger selection and the master mode selection blocks. Using one timer as prescaler for the other timer For example, to configure Timer 1 to act as a prescaler for Timer 2 (see Figure 45): ● Configure Timer 1 in Master mode so that it outputs a periodic trigger signal on each update event. Writing MMS = 010 in the TIM1_CR2 register causes a rising edge to be output on TRGO each time an update event is generated. ● To connect the TRGO output of Timer 1 to Timer 2, configure Timer 2 in slave mode using ITR0 as an internal trigger. Select this through the TS bits in the TIM2_SMCR register (writing TS = 000). ● Put the slave mode controller in external clock mode 1 (write SMS = 111 in the TIM2_SMCR register). This causes Timer 2 to be clocked by the rising edge of the periodic Timer 1 trigger signal (which corresponds to the Timer 1 counter overflow). ● Finally both timers must be enabled by setting their respective CEN bits (TIMx_CR1 register). Note: If OCy is selected on Timer 1 as trigger output (MMS = 1xx), its rising edge is used to clock the counter of Timer 2. Figure 45. Master/slave timer example TRGO1 UEV ITR1 Prescaler Counter SMS TS MMS TIMER 1 TIMER 2 Master mode control Slave mode control CK_PSC Prescaler Counter Clock Input selection trigger |
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