MPC8540 datasheet(132/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

2-14

Freescale Semiconductor

Memory Map

functional unit (for example, PCI). If a unit has error management registers, they are typically

placed starting at offset 0xE00 from the beginning of the block’s 4-Kbyte space, and any debug

registers are typically placed in the final 256 bytes of the unit’s register space starting at offset

0xF00.

General utilities registers are accessed as 32-bit quantities except for the DUART and I2C

registers, which are accessed as bytes.

NOTE

Refer to detailed register descriptions for each functional unit for

exact locations, sizes, and access requirements. Some blocks may

have exceptions to the above guidelines.

2.3.4

Interrupt Controller and CCSR

The programmable interrupt controller (PIC) registers are at offset 0x4_0000 from CCSRBAR,

see Figure 2-6. Its programming model follows the OpenPIC architecture. The interrupt controller

registers should only be accessed with 32-bit accesses.

Figure 2-6. PIC Mapping to Configuration, Control, and Status Memory Block

0x4 0000

Processor

Global Cfg

Timers

External IRQs

0x4 1100

0x5 1020

0x7 FFFF

PIC Registers

0x6 0000

0x5 0000

Internal IRQs

0x4 1000

0x4 1200

0x0 0000

Device-Specific

PIC

0xE 0000

0xF FFFF

CCSR Register Memory Block

0x4 0000

0x8 0000

General

Utilities

0xC 0000

RIO

Reserved

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