MPC8540 datasheet(128/1302 Pages) FREESCALE

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MPC8540 PowerQUICC III Integrated Host Processor Reference Manual, Rev. 1

2-10

Freescale Semiconductor

Memory Map

2.3

Configuration, Control, and Status Register Map

All of the memory mapped configuration, control, and status registers in the MPC8540 are

contained within a 1-Mbyte address region. To allow for flexibility, the configuration, control, and

status block is relocatable in the local address space. The local address map location of this register

block is controlled by the configuration, control, and status registers base address register

(CCSRBAR), see Section 4.3.1.1.2, “Configuration, Control, and Status Base Address Register

(CCSRBAR).” The default value for CCSRBAR is 4 Gbytes–9 Mbytes, or 0xFF70_0000.

NOTE

The configuration, control, and status window must not overlap a local

access window that maps to the DDR controller. Otherwise, undefined

behavior occurs.

An example of a top-level memory map with the default location of the configuration, control, and

status registers is shown in Figure 2-4.

Figure 2-4. Top-Level Register Map Example

Example Local

CCSRBAR (4G-9M)

4G-8M

Shaded area indicates locations not

allowed for CCSRBAR.

Only reserved if

Local Boot ROM

Memory Map

Memory

I/O

0x0_0000

Device-Specific

PIC

0xE_0000

0xF_FFFF

CCSR Register

Memory Block

0x4_0000

0x8_0000

General

Utilities

0xC_0000

Reserved

RapidIO

CCSR

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